公开(公告)号：US09064977B2

公开(公告)日：2015-06-23

申请号：US13591990

申请日：2012-08-22

申请人： Zhiwei Gong (Tony) ,  Michael B Vincent ,  Scott M Hayes ,  Jason R Wright

发明人： Zhiwei Gong (Tony) ,  Michael B Vincent ,  Scott M Hayes ,  Jason R Wright

IPC分类号： H01L29/72 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L25/00 ,  H01L25/03

CPC分类号： H01L25/0657 ,  H01L21/4853 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L25/03 ,  H01L25/105 ,  H01L25/50 ,  H01L2225/06551 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/00

摘要： Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of stacked microelectronic packages. In one embodiment, the method includes producing a partially-completed stacked microelectronic package including a package body having a vertical package sidewall, a plurality microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the vertical package sidewall. A flowable conductive material is applied on the vertical package sidewall and contacts the package edge conductors. Selected portions of the flowable conductive material are then removed to define, at least in part, electrically-isolated sidewall conductors electrically coupled to different ones of the package edge conductors.

摘要翻译： 提供了用于制造堆叠的微电子封装的方法的实施例，如堆叠的微电子封装的实施例。 在一个实施例中，该方法包括产生部分完成的叠层微电子封装，其包括具有垂直封装侧壁的封装体，嵌入封装主体内的多个微电子器件，以及电耦合到多个微电子器件的封装边缘导体， 垂直封装侧壁。 可流动的导电材料施加在垂直封装侧壁上，并与封装边缘导体接触。 然后去除可流动导电材料的选定部分，以至少部分地限定电隔离的侧壁导体，其电耦合到不同的封装边缘导体。

公开(公告)号：US20140054797A1

公开(公告)日：2014-02-27

申请号：US13591990

申请日：2012-08-22

申请人： Zhiwei Gong (Tony) ,  Michael B. Vincent ,  Scott M. Hayes ,  Jason R. Wright

发明人： Zhiwei Gong (Tony) ,  Michael B. Vincent ,  Scott M. Hayes ,  Jason R. Wright

IPC分类号： H01L23/48 ,  H01L21/50 ,  H01L21/78

CPC分类号： H01L25/0657 ,  H01L21/4853 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L25/03 ,  H01L25/105 ,  H01L25/50 ,  H01L2225/06551 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/00

摘要： Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of stacked microelectronic packages. In one embodiment, the method includes producing a partially-completed stacked microelectronic package including a package body having a vertical package sidewall, a plurality microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the vertical package sidewall. A flowable conductive material is applied on the vertical package sidewall and contacts the package edge conductors. Selected portions of the flowable conductive material are then removed to define, at least in part, electrically-isolated sidewall conductors electrically coupled to different ones of the package edge conductors.

摘要翻译： 提供了用于制造堆叠的微电子封装的方法的实施例，如堆叠的微电子封装的实施例。 在一个实施例中，该方法包括产生部分完成的叠层微电子封装，其包括具有垂直封装侧壁的封装体，嵌入封装主体内的多个微电子器件，以及电耦合到多个微电子器件的封装边缘导体， 垂直封装侧壁。 可流动的导电材料施加在垂直封装侧壁上，并与封装边缘导体接触。 然后去除可流动导电材料的选定部分，以至少部分地限定电隔离的侧壁导体，其电耦合到不同的封装边缘导体。

公开(公告)号：US20140070415A1

公开(公告)日：2014-03-13

申请号：US13610488

申请日：2012-09-11

申请人： Michael B. Vincent ,  Zhiwei Gong (Tony) ,  Scott M. Hayes ,  Douglas Mitchell

发明人： Michael B. Vincent ,  Zhiwei Gong (Tony) ,  Scott M. Hayes ,  Douglas Mitchell

IPC分类号： H01L23/52 ,  H01L21/768 ,  H01L21/56

CPC分类号： H01L21/76816 ,  H01L21/76814 ,  H01L23/485 ,  H01L23/525 ,  H01L23/528 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/0231 ,  H01L2224/02375 ,  H01L2224/04105 ,  H01L2924/12042 ,  H01L2924/00

摘要： Embodiments of a microelectronic package including at least one trench via are provided, as are embodiments of a method for fabricating such a microelectronic package. In one embodiment, the method includes the step of depositing a dielectric layer over a first microelectronic device having a plurality of contact pads, which are covered by the dielectric layer. A trench via is formed in the dielectric layer to expose the plurality of contact pads therethrough. The trench via is formed to include opposing crenulated sidewalls having a plurality of recesses therein. The plurality of contact pads exposed through the trench via are then sputter etched. A plurality of interconnect lines is formed over the dielectric layer, each of which is electrically coupled to a different one of the plurality of contact pads.

摘要翻译： 提供了包括至少一个沟槽通孔的微电子封装的实施例，如制造这种微电子封装的方法的实施例。 在一个实施例中，该方法包括在第一微电子器件上沉积介电层的步骤，该第一微电子器件具有被介电层覆盖的多个接触焊盘。 沟槽通孔形成在电介质层中以暴露多个接触焊盘。 沟槽通孔被形成为包括在其中具有多个凹部的相对的有齿的侧壁。 然后溅射蚀刻通过沟槽通孔暴露的多个接触焊盘。 多个互连线形成在电介质层上，每个互连线电耦合到多个接触焊盘中的不同的一个。