公开(公告)号：US07525779B2

公开(公告)日：2009-04-28

申请号：US11205378

申请日：2005-08-17

申请人： Zi-Ping Chen ,  Ming-Dou Ker

发明人： Zi-Ping Chen ,  Ming-Dou Ker

IPC分类号： H02H9/00

CPC分类号： H01L27/0255 ,  H01L29/7436

摘要： Diode strings and electrostatic discharge circuits characterized by low current leakage. Each diode region provides a diode and has first and second regions. The first region is of a first conductive type and formed on a substrate, acting as a first electrode of a diode. The second region is of a second conductive type opposite to the first conductive type, formed in the first region and acting as a second electrode of a corresponding diode. The diodes are forward connected in series to form major anode and cathode of the diode string. An isolation region is of the second conductive type to isolate those diode regions. A bias resistor is connected between the isolation region and a first power line. During normal operation, the voltage of the first power line is not within the range between the voltages of the major anode and cathode.

摘要翻译： 具有低电流泄漏特性的二极管串和静电放电电路。 每个二极管区域提供二极管并且具有第一和第二区域。 第一区域是第一导电类型并且形成在用作二极管的第一电极的衬底上。 第二区域是与第一导电类型相反的第二导电类型，形成在第一区域中并用作相应二极管的第二电极。 二极管串联连接以形成二极管串的主要阳极和阴极。 隔离区域是隔离这些二极管区域的第二导电类型。 偏置电阻连接在隔离区和第一电源线之间。 在正常操作期间，第一电源线的电压不在主阳极和阴极的电压之间的范围内。

公开(公告)号：US06920026B2

公开(公告)日：2005-07-19

申请号：US10426625

申请日：2003-05-01

申请人： Zi-Ping Chen ,  Chyh-Yih Chang ,  Ming-Dou Ker

发明人： Zi-Ping Chen ,  Chyh-Yih Chang ,  Ming-Dou Ker

IPC分类号： H01L27/02 ,  H02H9/00

CPC分类号： H01L27/0266

摘要： An ESD protection circuit with whole-chip ESD protection. A plurality of ESD protection devices, apart from an ESD detection circuit, can be MOS transistors connected between the input/output pads and the VDD/VSS lines or a power rail clamp circuit between the VDD and VSS lines. The ESD detection circuit is connected between the VDD and VSS lines. When an ESD event occurs and an ESD current is bypassed to the power line, the ESD detection circuit generates a plurality of enabling signals to simultaneously enable the ESD protection devices, which provides a plurality of discharge paths to bypass the ESD current.

摘要翻译： 具有全芯片ESD保护的ESD保护电路。 除了ESD检测电路之外，多个ESD保护器件可以是连接在输入/输出焊盘与VDD / VSS线之间的MOS晶体管，也可以是连接在VDD和VSS线之间的电源轨钳位电路。 ESD检测电路连接在VDD和VSS线之间。 当ESD事件发生并且ESD电流旁路到电力线时，ESD检测电路产生多个使能信号，以同时启用ESD保护装置，其提供多个放电路径来绕过ESD电流。

公开(公告)号：US20060043489A1

公开(公告)日：2006-03-02

申请号：US11004348

申请日：2004-12-03

申请人： Zi-Ping Chen ,  Ming-Dou Ker

发明人： Zi-Ping Chen ,  Ming-Dou Ker

IPC分类号： H01L23/62

CPC分类号： H01L27/0255

摘要： A diode with low substrate current leakage and suitable for BiCMOS process technology. A buried layer is formed on a semiconductor substrate. A connection region and well contact the buried layer. Isolation regions are adjacent to two sides of the buried layer, each deeper than the buried layer. The isolation regions and the buried layer isolate the connection zone and the well from the substrate. The first doped region in the well is a first electrode. The well and the connection region are electrically connected, acting as a second electrode.

摘要翻译： 具有低衬底电流泄漏并适用于BiCMOS工艺技术的二极管。 在半导体衬底上形成掩埋层。 连接区域和阱接触埋层。 隔离区域与埋层的两侧相邻，每一个都比埋层更深。 隔离区域和掩埋层将连接区域和阱与衬底隔离。 阱中的第一掺杂区域是第一电极。 阱和连接区域电连接，用作第二电极。

公开(公告)号：US20080203424A1

公开(公告)日：2008-08-28

申请号：US12118364

申请日：2008-05-09

申请人： Zi-Ping Chen ,  Ming-Dou Ker

发明人： Zi-Ping Chen ,  Ming-Dou Ker

IPC分类号： H01L33/00 ,  H01L23/62

CPC分类号： H01L27/0255

摘要： A diode with low substrate current leakage and suitable for BiCMOS process technology. A buried layer is formed on a semiconductor substrate. A connection region and well contact the buried layer. Isolation regions are adjacent to two sides of the buried layer, each deeper than the buried layer. The isolation regions and the buried layer isolate the connection zone and the well from the substrate. The first doped region in the well is a first electrode. The well and the connection region are electrically connected, acting as a second electrode.

摘要翻译： 具有低衬底电流泄漏并适用于BiCMOS工艺技术的二极管。 在半导体衬底上形成掩埋层。 连接区域和阱接触埋层。 隔离区域与埋层的两侧相邻，每一个都比埋层更深。 隔离区域和掩埋层将连接区域和阱与衬底隔离。 阱中的第一掺杂区域是第一电极。 阱和连接区域电连接，用作第二电极。

公开(公告)号：US20060044719A1

公开(公告)日：2006-03-02

申请号：US11205378

申请日：2005-08-17

申请人： Zi-Ping Chen ,  Ming-Dou Ker

发明人： Zi-Ping Chen ,  Ming-Dou Ker

IPC分类号： H02H9/00

CPC分类号： H01L27/0255 ,  H01L29/7436

摘要： Diode strings and electrostatic discharge circuits characterized by low current leakage. Each diode region provides a diode and has first and second regions. The first region is of a first conductive type and formed on a substrate, acting as a first electrode of a diode. The second region is of a second conductive type opposite to the first conductive type, formed in the first region and acting as a second electrode of a corresponding diode. The diodes are forward connected in series to form major anode and cathode of the diode string. An isolation region is of the second conductive type to isolate those diode regions. A bias resistor is connected between the isolation region and a first power line. During normal operation, the voltage of the first power line is not within the range between the voltages of the major anode and cathode.

公开(公告)号：US07696580B2

公开(公告)日：2010-04-13

申请号：US12118364

申请日：2008-05-09

申请人： Zi-Ping Chen ,  Ming-Dou Ker

发明人： Zi-Ping Chen ,  Ming-Dou Ker

IPC分类号： H01L27/06

CPC分类号： H01L27/0255

摘要： A diode with low substrate current leakage and suitable for BiCMOS process technology. A buried layer is formed on a semiconductor substrate. A connection region and well contact the buried layer. Isolation regions are adjacent to two sides of the buried layer, each deeper than the buried layer. The isolation regions and the buried layer isolate the connection zone and the well from the substrate. The first doped region in the well is a first electrode. The well and the connection region are electrically connected, acting as a second electrode.

摘要翻译： 具有低衬底电流泄漏并适用于BiCMOS工艺技术的二极管。 在半导体衬底上形成埋层。 连接区域和阱接触埋层。 隔离区域与埋层的两侧相邻，每一个都比埋层更深。 隔离区域和掩埋层将连接区域和阱与衬底隔离。 阱中的第一掺杂区域是第一电极。 阱和连接区域电连接，用作第二电极。

公开(公告)号：US07372109B2

公开(公告)日：2008-05-13

申请号：US11004348

申请日：2004-12-03

申请人： Zi-Ping Chen ,  Ming-Dou Ker

发明人： Zi-Ping Chen ,  Ming-Dou Ker

IPC分类号： H01L29/76

CPC分类号： H01L27/0255

摘要： A diode with low substrate current leakage and suitable for BiCMOS process technology. A buried layer is formed on a semiconductor substrate. A connection region and well contact the buried layer. Isolation regions are adjacent to two sides of the buried layer, each deeper than the buried layer. The isolation regions and the buried layer isolate the connection zone and the well from the substrate. The first doped region in the well is a first electrode. The well and the connection region are electrically connected, acting as a second electrode.

摘要翻译： 具有低衬底电流泄漏并适用于BiCMOS工艺技术的二极管。 在半导体衬底上形成埋层。 连接区域和阱接触埋层。 隔离区域与埋层的两侧相邻，每一个都比埋层更深。 隔离区域和掩埋层将连接区域和阱与衬底隔离。 阱中的第一掺杂区域是第一电极。 阱和连接区域电连接，用作第二电极。

公开(公告)号：US08552530B2

公开(公告)日：2013-10-08

申请号：US12848531

申请日：2010-08-02

申请人： Kun-Hsien Lin ,  Zi-Ping Chen ,  Che-Hao Chuang ,  Ryan Hsin-Chin Jiang

发明人： Kun-Hsien Lin ,  Zi-Ping Chen ,  Che-Hao Chuang ,  Ryan Hsin-Chin Jiang

IPC分类号： H01L29/06

CPC分类号： H01L27/0259

摘要： A vertical transient voltage suppressor for protecting an electronic device is disclosed. The vertical transient voltage includes a conductivity type substrate having highly doping concentration; a first type lightly doped region is arranged on the conductivity type substrate, wherein the conductivity type substrate and the first type lightly doped region respectively belong to opposite types; a first type heavily doped region and a second type heavily doped region are arranged in the first type lightly doped region, wherein the first and second type heavily doped regions and the conductivity type substrate belong to same types; and a deep first type heavily doped region is arranged on the conductivity type substrate and neighbors the first type lightly doped region, wherein the deep first type heavily doped region and the first type lightly doped region respectively belong to opposite types, and wherein the deep first type heavily doped region is coupled to the first type heavily doped region.

摘要翻译： 公开了一种用于保护电子设备的垂直瞬态电压抑制器。 垂直瞬变电压包括具有高掺杂浓度的导电型衬底; 导电型衬底上布置有第一类型轻掺杂区域，其中导电类型衬底和第一类型轻掺杂区域分别属于相反类型; 第一类型重掺杂区和第二类重掺杂区布置在第一类型轻掺杂区域中，其中第一和第二类型重掺杂区和导电类型衬底属于相同类型; 并且深度第一类型重掺杂区域布置在导电类型衬底上并且与第一类型轻掺杂区域相邻，其中深第一类型重掺杂区域和第一类型轻掺杂区域分别属于相反类型，并且其中深第一类型重掺杂区域 型重掺杂区域耦合到第一类型重掺杂区域。

公开(公告)号：US08304838B1

公开(公告)日：2012-11-06

申请号：US13216016

申请日：2011-08-23

申请人： Zi-Ping Chen ,  Tung-Yang Chen ,  Kun-Hsien Lin ,  Ryan Hsin-Chin Jiang

发明人： Zi-Ping Chen ,  Tung-Yang Chen ,  Kun-Hsien Lin ,  Ryan Hsin-Chin Jiang

IPC分类号： H01L21/00

CPC分类号： H01L27/0255

摘要： An electrostatic discharge protection device structure is disclosed, which comprises a semiconductor substrate and an N-type epitaxial layer arranged on the semiconductor substrate. At least one snapback cascade structure is arranged in the N-type epitaxial layer, wherein the snapback cascade structure further comprises first and second P-type wells arranged in the N-type epitaxial layer. First and second heavily doped areas arranged in the first P-type well respectively belong to opposite types. And, third and fourth heavily doped areas arranged in the second P-type well respectively belong to opposite types, wherein the second and third heavily doped areas respectively belong to opposite types and are electrically connected with each other. When the first heavily doped area receives an ESD signal, an ESD current flows from the first heavily doped area to the fourth heavily doped area through the first P-type well, the N-type epitaxial layer, and the second P-type well.

摘要翻译： 公开了一种静电放电保护器件结构，其包括半导体衬底和布置在半导体衬底上的N型外延层。 在N型外延层中布置有至少一个快速反应级联结构，其中快速回退级联结构还包括布置在N型外延层中的第一和第二P型阱。 排列在第一P型井中的第一和第二重掺杂区域分别属于相反的类型。 并且，排列在第二P型阱中的第三和第四重掺杂区域分别属于相反的类型，其中第二和第三重掺杂区域分别属于相反的类型并且彼此电连接。 当第一重掺杂区域接收到ESD信号时，ESD电流通过第一P型阱，N型外延层和第二P型阱从第一重掺杂区流动到第四重掺杂区。

公开(公告)号：US08217421B2

公开(公告)日：2012-07-10

申请号：US12840749

申请日：2010-07-21

申请人： Zi-Ping Chen ,  Kun-Hsien Lin ,  Ryan Hsin-Chin Jiang

发明人： Zi-Ping Chen ,  Kun-Hsien Lin ,  Ryan Hsin-Chin Jiang

IPC分类号： H01L29/66

CPC分类号： H01L27/0259

摘要： A new ESD protection device with an integrated-circuit vertical transistor structure is disclosed, which includes a heavily doped p-type substrate (P+ substrate), a n-type well (N well) in the P+ substrate, a heavily doped p-type diffusion (P+ diffusion) in the N well, a heavily doped n-type diffusion (N+ diffusion) in the N well, and a p-type well (P well) surrounding the N well in the P+ substrate. A bond pad is connected to both the P+ and N+ diffusions, and a ground is coupled to the P+ substrate. Another P+ diffusion is implanted in the N well or another N+ diffusion is implanted in the P well to form a Zener diode, which behaves as a trigger for the PNP transistor when a positive ESD zaps. A parasitic diode is formed at the junction between the P+ substrate and the N well, to bypass a negative ESD stress on the bond pad.

摘要翻译： 公开了一种具有集成电路垂直晶体管结构的新型ESD保护器件，其包括重掺杂p型衬底（P +衬底），P +衬底中的n型阱（N阱），重掺杂p型衬底 N阱中的扩散（P +扩散），N阱中的重掺杂n型扩散（N +扩散）以及P +衬底中N阱周围的p型阱（P阱）。 接合焊盘连接到P +和N +扩散两者，并且接地耦合到P +衬底。 将另一个P +扩散注入到N阱中，或者将另一个N +扩散注入到P阱中以形成齐纳二极管，当正ESD成像时，其作为PNP晶体管的触发器。 在P +衬底和N阱之间的接合处形成寄生二极管，以绕过接合焊盘上的负ESD应力。