公开(公告)号：US08400863B1

公开(公告)日：2013-03-19

申请号：US12860734

申请日：2010-08-20

申请人： Zun Yang Tan ,  Wei Yee Koay ,  Boon Jin Ang ,  Tat Mun Lui ,  Eu Geen Chew

发明人： Zun Yang Tan ,  Wei Yee Koay ,  Boon Jin Ang ,  Tat Mun Lui ,  Eu Geen Chew

IPC分类号： G11C8/00

CPC分类号： G11C8/12

摘要： Circuits for a memory array and a method of operating a configurable memory block are disclosed. An embodiment of the disclosed memory circuits includes a first memory block coupled to a second memory block to form an array of memory blocks. Each of the memory blocks has multiple bit lines with a dedicated address decoder coupled to the bit lines from each of the memory blocks. Switches are placed in between the first and second memory blocks such that each of the bit lines from the first memory block is connected to a corresponding bitline from the second memory block through one of the switches. The switches may be used to either connect the second memory block to the first memory block or disconnect the second memory block from the first memory block.

摘要翻译： 公开了用于存储器阵列的电路和操作可配置存储器块的方法。 所公开的存储器电路的实施例包括耦合到第二存储器块以形成存储器块阵列的第一存储器块。 每个存储器块具有多个位线，其中专用地址解码器耦合到来自每个存储器块的位线。 开关被放置在第一和第二存储器块之间，使得来自第一存储器块的每个位线通过其中一个开关连接到来自第二存储器块的相应位线。 交换机可以用于将第二存储器块连接到第一存储器块或将第二存储器块与第一存储器块断开。

公开(公告)号：US09680773B1

公开(公告)日：2017-06-13

申请号：US13245790

申请日：2011-09-26

申请人： Zun Yang Tan ,  Tat Mun Lui ,  Boon Jin Ang ,  Chiang Wei Lee ,  Richard Jin Guan Saw ,  Want Sent Khor

发明人： Zun Yang Tan ,  Tat Mun Lui ,  Boon Jin Ang ,  Chiang Wei Lee ,  Richard Jin Guan Saw ,  Want Sent Khor

IPC分类号： H04L12/861 ,  G06F5/12 ,  G06F1/32 ,  G11C5/14

CPC分类号： H04L49/9005 ,  G06F1/3225 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3278 ,  G06F1/3287 ,  G06F5/12 ,  G11C5/148 ,  Y02D10/14 ,  Y02D10/157

摘要： One embodiment relates to an integrated circuit which includes a method of dynamically adjusting a receive buffer in an integrated circuit. A fixed-size buffer circuit of the receive buffer is used to buffer data received by way of a serial interface circuit. The performance of the serial interface circuit are monitored. The receive buffer is dynamically extended based on said performance. Other embodiments, aspects, and features are also disclosed.