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公开(公告)号：US07807563B2
公开(公告)日：2010-10-05
申请号：US11786770
申请日：2007-04-12
申请人： Zvonimir Gabric , Werner Pamler , Guenther Schindler , Gernot Steinlesberger , Andreas Stich , Martin Traving , Eugen Unger
发明人： Zvonimir Gabric , Werner Pamler , Guenther Schindler , Gernot Steinlesberger , Andreas Stich , Martin Traving , Eugen Unger
IPC分类号： H01L23/58
CPC分类号： H01L23/5222 , H01L21/7682 , H01L2924/0002 , H01L2924/00
摘要： In a method for manufacturing a layer arrangement, a plurality of electrically conductive structures are embedded in a substrate. Material of the substrate is removed at least between adjacent electrically conductive structures. An interlayer is formed on at least one portion of sidewalls of each of the electrically conductive structures. A first layer is formed on the interlayer where an upper partial region of the interlayer remaining free of a covering with the first layer. An electrically insulating second layer is formed selectively on that partial region of the interlayer which is free of the first layer, in such a way that the electrically insulating second layer bridges adjacent electrically conductive structures such that air gaps are formed between adjacent electrically conductive structures.
摘要翻译： 在制造层布置的方法中，多个导电结构嵌入基板中。 至少在相邻的导电结构之间去除衬底的材料。 在每个导电结构的侧壁的至少一部分上形成中间层。 第一层形成在中间层上，其中层间的上部分区域保留没有覆盖物与第一层。 选择性地在中间层的不含第一层的部分区域上形成电绝缘的第二层，使得电绝缘的第二层桥接相邻的导电结构，使得在相邻的导电结构之间形成气隙。
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公开(公告)号：US20070246831A1
公开(公告)日：2007-10-25
申请号：US11786770
申请日：2007-04-12
申请人： Zvonimir Gabric , Werner Pamler , Guenther Schindler , Gernot Steinlesberger , Andreas Stich , Martin Traving , Eugen Unger
发明人： Zvonimir Gabric , Werner Pamler , Guenther Schindler , Gernot Steinlesberger , Andreas Stich , Martin Traving , Eugen Unger
IPC分类号： H01L23/52
CPC分类号： H01L23/5222 , H01L21/7682 , H01L2924/0002 , H01L2924/00
摘要： In a method for manufacturing a layer arrangement, a plurality of electrically conductive structures are embedded in a substrate. Material of the substrate is removed at least between adjacent electrically conductive structures. An interlayer is formed on at least one portion of sidewalls of each of the electrically conductive structures. A first layer is formed on the interlayer where an upper partial region of the interlayer remaining free of a covering with the first layer. An electrically insulating second layer is formed selectively on that partial region of the interlayer which is free of the first layer, in such a way that the electrically insulating second layer bridges adjacent electrically conductive structures such that air gaps are formed between adjacent electrically conductive structures.
摘要翻译： 在制造层布置的方法中，多个导电结构嵌入基板中。 至少在相邻的导电结构之间去除衬底的材料。 在每个导电结构的侧壁的至少一部分上形成中间层。 第一层形成在中间层上，其中层间的上部分区域保留没有覆盖物与第一层。 选择性地在中间层的不含第一层的部分区域上形成电绝缘的第二层，使得电绝缘的第二层桥接相邻的导电结构，使得在相邻的导电结构之间形成气隙。
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公开(公告)号：US20070120263A1
公开(公告)日：2007-05-31
申请号：US11506570
申请日：2006-08-18
IPC分类号： H01L23/48
CPC分类号： H01L21/7682
摘要： A conductor track arrangement includes a substrate, at least two conductor tracks, a cavity and a resist layer that covers the conductor tracks and closes off the cavity. By forming carrier tracks with a width less than a width of the conductor tracks, air gaps can also be formed laterally underneath the conductor tracks for reducing the coupling capacitances and the signal delays in a self-aligning manner.
摘要翻译： 导体轨道布置包括衬底，至少两个导体轨道，空腔和覆盖导体轨道并封闭空腔的抗蚀剂层。 通过形成宽度小于导体轨道的宽度的载体轨道，还可以在导体轨道下方横向形成气隙，以便以自对准方式减小耦合电容和信号延迟。
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4.发明授权Plasma excited chemical vapor deposition method silicon/oxygen/nitrogen-containing-material and layered assembly 有权等离子体激发化学气相沉积法硅/氧/含氮材料和分层组装公开(公告)号：US07755160B2
公开(公告)日：2010-07-13
申请号：US10586788
申请日：2005-01-22
IPC分类号： H01L21/314 , H01L21/469
CPC分类号： H01L21/764 , C23C16/308 , H01L21/3145 , H01L21/76801 , H01L21/76807 , H01L21/7682 , H01L23/5222 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A method for producing a layer arrangement is disclosed. A layer of oxygen material and nitrogen material is formed over a substrate that has a plurality of electrically conductive structures and/or over a part of a surface of the electrically conductive structures. The layer is formed using a plasma-enhanced chemical vapor deposition process with nitrogen material being supplied during the supply of silicon material and oxygen material by means of an organic silicon precursor material. The layer of oxygen material and nitrogen material is formed in such a manner that an area free of material remains between the electrically conductive structures. An intermediate layer including an electrically insulating material is formed over the layer of oxygen material and nitrogen material. A covering layer is selectively formed over the intermediate layer such that the area free of material between the electrically conductive structures is sealed from the environment and forms a cavity.
摘要翻译： 公开了一种制造层布置的方法。 在具有多个导电结构和/或导电结构的一部分表面上的衬底上形成一层氧材料和氮材料。 使用等离子体增强化学气相沉积工艺形成该层，其中在通过有机硅前体材料供应硅材料和氧材料期间供给氮材料。 氧材料层和氮材料层以这样的方式形成，使得在导电结构之间保留没有材料的区域。 在氧材料层和氮材料层上形成包括电绝缘材料的中间层。 在中间层上选择性地形成覆盖层，使得在导电结构之间没有材料的区域与环境密封并形成空腔。
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5.发明申请Plasma Excited Chemical Vapor Deposition Method Silicon/Oxygen/Nitrogen-Containing-Material and Layered Assembly 有权等离子体激发化学气相沉积方法硅/氧/含氮材料和分层组装公开(公告)号：US20080308898A1
公开(公告)日：2008-12-18
申请号：US10586788
申请日：2005-01-22
IPC分类号： H01L21/314 , H01L23/58
CPC分类号： H01L21/764 , C23C16/308 , H01L21/3145 , H01L21/76801 , H01L21/76807 , H01L21/7682 , H01L23/5222 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A method for producing a layer arrangement is disclosed. A layer of oxygen material and nitrogen material is formed over a substrate that has a plurality of electrically conductive structures and/or over a part of a surface of the electrically conductive structures. The layer is formed using a plasma-enhanced chemical vapor deposition process with nitrogen material being supplied during the supply of silicon material and oxygen material by means of an organic silicon precursor material. The layer of oxygen material and nitrogen material is formed in such a manner that an area free of material remains between the electrically conductive structures. An intermediate layer including an electrically insulating material is formed over the layer of oxygen material and nitrogen material. A covering layer is selectively formed over the intermediate layer such that the area free of material between the electrically conductive structures is sealed from the environment and forms a cavity.
摘要翻译： 公开了一种制造层布置的方法。 在具有多个导电结构和/或导电结构的一部分表面上的衬底上形成一层氧材料和氮材料。 使用等离子体增强化学气相沉积工艺形成该层，其中在通过有机硅前体材料供应硅材料和氧材料期间供给氮材料。 氧材料层和氮材料层以这样的方式形成，使得在导电结构之间保留没有材料的区域。 在氧材料层和氮材料层上形成包括电绝缘材料的中间层。 在中间层上选择性地形成覆盖层，使得在导电结构之间没有材料的区域与环境密封并形成空腔。
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公开(公告)号：US20060199368A1
公开(公告)日：2006-09-07
申请号：US11362269
申请日：2006-02-22
IPC分类号： H01L21/4763 , H01L23/48
CPC分类号： H01L21/7681 , H01L21/7682 , H01L23/5222 , H01L23/53295 , H01L27/10885 , H01L2924/0002 , H01L2924/00
摘要： An interconnect arrangement and fabrication method are described. The interconnect arrangement includes an electrically conductive mount substrate, a dielectric layer formed on the mount substrate, and an electrically conductive interconnect formed on the dielectric layer. At least a portion of the dielectric layer under the interconnect contains a cavity. To fabricate the interconnect arrangement, a sacrificial layer is formed on the mount substrate and the interconnect layer is formed on the sacrificial layer. The interconnect layer and the sacrificial layer are structured to produce a structured interconnect on the structured sacrificial layer. A porous dielectric layer is formed on a surface of the mount substrate and of the structured interconnect as well as the sacrificial layer. The sacrificial layer is then removed to form the cavity under the interconnect.
摘要翻译： 描述了互连装置和制造方法。 互连装置包括导电安装基板，形成在安装基板上的电介质层和形成在电介质层上的导电布线。 互连下方的电介质层的至少一部分包含空腔。 为了制造互连布置，在安装基板上形成牺牲层，并且在牺牲层上形成互连层。 互连层和牺牲层被构造成在结构化牺牲层上产生结构化互连。 在安装基板和结构化互连的表面以及牺牲层上形成多孔电介质层。 然后去除牺牲层以在互连下形成空腔。
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公开(公告)号：US08877631B2
公开(公告)日：2014-11-04
申请号：US13110022
申请日：2011-05-18
IPC分类号： H01L21/4763 , H01L23/522 , H01L23/532 , H01L21/768 , H01L27/108
CPC分类号： H01L21/7681 , H01L21/7682 , H01L23/5222 , H01L23/53295 , H01L27/10885 , H01L2924/0002 , H01L2924/00
摘要： An interconnect arrangement and fabrication method are described. The interconnect arrangement includes an electrically conductive mount substrate, a dielectric layer formed on the mount substrate, and an electrically conductive interconnect formed on the dielectric layer. At least a portion of the dielectric layer under the interconnect contains a cavity. To fabricate the interconnect arrangement, a sacrificial layer is formed on the mount substrate and the interconnect layer is formed on the sacrificial layer. The interconnect layer and the sacrificial layer are structured to produce a structured interconnect on the structured sacrificial layer. A porous dielectric layer is formed on a surface of the mount substrate and of the structured interconnect as well as the sacrificial layer. The sacrificial layer is then removed to form the cavity under the interconnect.
摘要翻译： 描述了互连装置和制造方法。 互连装置包括导电安装基板，形成在安装基板上的电介质层和形成在电介质层上的导电布线。 互连下方的电介质层的至少一部分包含空腔。 为了制造互连布置，在安装基板上形成牺牲层，并且在牺牲层上形成互连层。 互连层和牺牲层被构造成在结构化牺牲层上产生结构化互连。 在安装基板和结构化互连的表面以及牺牲层上形成多孔电介质层。 然后去除牺牲层以在互连下形成空腔。
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公开(公告)号：US20070111431A1
公开(公告)日：2007-05-17
申请号：US11540502
申请日：2006-09-29
IPC分类号： H01L21/8242 , H01L29/94
摘要： An MIM capacitor includes a first capacitor electrode, which is formed in the surface of a first intermediate dielectric, a second intermediate dielectric, which is formed on the first intermediate dielectric and has an opening that exposes the first capacitor electrode, and a first electrically conducting diffusion barrier layer, which is formed on the surface of the exposed first capacitor electrode. On the diffusion barrier layer and on the side walls of the opening there is also formed a capacitor dielectric and a second capacitor electrode on top.
摘要翻译： MIM电容器包括形成在第一中间电介质的表面中的第一电容器电极，形成在第一中间电介质上并具有暴露第一电容器电极的开口的第二中间电介质，以及第一导电 扩散阻挡层，其形成在暴露的第一电容器电极的表面上。 在扩散阻挡层和开口的侧壁上，还在顶部形成电容电介质和第二电容器电极。
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公开(公告)号：US20070216030A1
公开(公告)日：2007-09-20
申请号：US11675400
申请日：2007-02-15
IPC分类号： H01L23/48
CPC分类号： H01L23/5223 , H01L21/76838 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit having a multilayer capacitance arrangement and a method for producing an integrated circuit having a multilayer capacitance arrangement are disclosed.
摘要翻译： 公开了具有多层电容布置的集成电路和具有多层电容布置的集成电路的制造方法。
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公开(公告)号：US20120100689A1
公开(公告)日：2012-04-26
申请号：US13342120
申请日：2012-01-02
IPC分类号： H01L21/02
摘要： An MIM capacitor includes a first capacitor electrode, which is formed in the surface of a first intermediate dielectric, a second intermediate dielectric, which is formed on the first intermediate dielectric and has an opening that exposes the first capacitor electrode, and a first electrically conducting diffusion barrier layer, which is formed on the surface of the exposed first capacitor electrode. On the diffusion barrier layer and on the side walls of the opening there is also formed a capacitor dielectric and a second capacitor electrode on top.
摘要翻译： MIM电容器包括形成在第一中间电介质的表面中的第一电容器电极，形成在第一中间电介质上并具有暴露第一电容器电极的开口的第二中间电介质，以及第一导电 扩散阻挡层，其形成在暴露的第一电容器电极的表面上。 在扩散阻挡层和开口的侧壁上，还在顶部形成电容器电介质和第二电容器电极。
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