公开(公告)号：US20180164266A1

公开(公告)日：2018-06-14

申请号：US15841848

申请日：2017-12-14

Applicant: dSPACE digital signal processing and control engineering GmbH

Inventor： Dirk HASSE ,  Michael WARTIG

IPC: G01N33/00 ,  G01N27/41 ,  G01N27/416

CPC classification number: G01N33/0006 ,  F02D41/1456 ,  F02D41/1495 ,  F02D2041/1437 ,  G01M15/104 ,  G01N27/41 ,  G01N27/4163

Abstract: A test bench for a control system for controlling a wideband lambda sensor, which is configured to calculate an actual value, which represents an oxygen concentration in a measuring gap of a wideband lambda sensor or an indicator value from which the oxygen concentration can be derived, with consideration of a current generated by a pump voltage in an electrical circuit. In order to simulate the electrical response of a pump cell of the wideband lambda sensor, a first diode and a second diode are connected in parallel in the electrical circuit such that a current flows through the first diode at a first polarity of the pump voltage and a current flows through the second diode at a second polarity of the pump voltage.

公开(公告)号：US20140333344A1

公开(公告)日：2014-11-13

申请号：US14275284

申请日：2014-05-12

Applicant: dSPACE digital signal processing and control engineering GmbH

Inventor： Dirk HASSE ,  Robert POLNAU

IPC: H03K19/0175

CPC classification number: H03K19/017509 ,  G06F13/4291 ,  H03K19/0175 ,  H03K19/17732 ,  H03K19/17744

Abstract: A method for implementing an adaptive interface between at least one FPGA with at least one FPGA application and at least one I/O module, which are designed as the corresponding sender side or receiver side, for connection to the FPGA, whereby a serial interface is formed between the at least one FPGA and the at least one I/O module, comprising the steps of configuring a maximum number of registers to be transmitted for each FPGA application, configuring a shared, fixed register width for all registers, setting an enable signal on the sender side for the registers to be transmitted out of the maximum number of registers to be transmitted, transmitting the enable signal from the sender side to the receiver side, and transmitting the registers, for which the enable signal is set, from the sender side to the receiver side.

Abstract translation: 一种在至少一个FPGA与至少一个FPGA应用之间实现自适应接口的方法和被设计为相应的发送机侧或接收机侧的至少一个I / O模块，用于连接到FPGA，由此串行接口是 形成在所述至少一个FPGA和所述至少一个I / O模块之间，包括以下步骤：配置要针对每个FPGA应用发送的最大寄存器数量，为所有寄存器配置共享固定寄存器宽度，设置使能信号 在发送侧，要发送的寄存器的最大数量的寄存器发送，将发送端发送到接收端，并从发送方发送启用信号的寄存器 侧到接收机侧。

公开(公告)号：US20150153413A1

公开(公告)日：2015-06-04

申请号：US14556830

申请日：2014-12-01

Applicant: dSPACE digital signal processing and control engineering GmbH

Inventor： Dirk HASSE ,  Peter SCHEIBELHUT ,  Robert POLNAU

IPC: G01R31/319 ,  G01R31/00

CPC classification number: G01R31/31917 ,  G01R31/005 ,  G06F11/26

Abstract: An apparatus for testing an electrical component, having a simulation unit for producing a simulation signal, a plurality of test units, and at least one electrical connecting device, whereby the simulation unit and the plurality of test units are connected or connectable to each other in an electrically conductive fashion via the at least one connecting device, and the at least one connecting device has at least one electrical switch device, which is situated to make or break an electrical connection between the plurality of test units.

Abstract translation: 一种用于测试电气部件的装置，具有用于产生模拟信号的模拟单元，多个测试单元和至少一个电连接装置，由此模拟单元和多个测试单元彼此连接或可连接 经由所述至少一个连接装置的导电方式，并且所述至少一个连接装置具有至少一个电气开关装置，所述至少一个电气开关装置被设置成使所述多个测试装置之间的电连接形成或断开。