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Patent Agency Ranking
公开(公告)号：US20160335101A1
公开(公告)日：2016-11-17
申请号：US15151746
申请日：2016-05-11
Inventor： Jochen SAUER , Robert LEINFELLNER , Matthias KLEMM , Thorsten BREHM , Robert POLNAU , Matthias SCHMITZ
CPC classification number: G06F13/102 , G06F9/4411 , G06F9/44505 , G06F13/126 , G06F13/20 , G06F13/385 , G06F13/4022 , G06F13/4068 , G06F13/4072 , G06F15/7885 , G11C8/18
Abstract: A method for configuring an interface unit of a computer system with a first processor and a second processor stored in the interface unit. A data link is set up between the first processor and the second processor. A peripheral of the computer system is configured to store input data in an input data channel and to read output data from an output data channel, and the second processor is configured to read the input data from the input data channel and to store output data in the output data channel. A sequence of processor commands for the second processor is created such that a number of subsequences is created.
Abstract translation: 一种用于配置具有存储在接口单元中的第一处理器和第二处理器的计算机系统的接口单元的方法。 在第一处理器和第二处理器之间建立数据链路。 计算机系统的外围设备被配置为将输入数据存储在输入数据通道中并从输出数据通道读取输出数据，并且第二处理器被配置为从输入数据通道读取输入数据并将输出数据存储在 输出数据通道。 创建用于第二处理器的处理器命令的序列，使得创建多个子序列。
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公开(公告)号：US20160335203A1
公开(公告)日：2016-11-17
申请号：US15151767
申请日：2016-05-11
Inventor： Jochen SAUER , Robert LEINFELLNER , Matthias KLEMM , Thorsten BREHM , Robert POLNAU , Matthias SCHMITZ
CPC classification number: G06F13/102 , G06F9/4411 , G06F9/44505 , G06F13/126 , G06F13/20 , G06F13/385 , G06F13/4022 , G06F13/4068 , G06F13/4072 , G06F15/7885 , G11C8/18
Abstract: An interface unit for data exchange between a first processor of a computer system and a peripheral environment. The interface unit has a number of input data channels for receiving input data from the peripheral environment and a first access management unit. The access management unit is configured to receive a request for providing the input data, stored in the number of input data channels, from a first interface processor stored in the interface unit and from a second interface processor stored in the interface unit and to provide or not to provide the input data, stored in the number of input data channels, to the first interface processor and the second interface processor. A first priority and a second priority can be stored in the first access management unit.
Abstract translation: 一种用于在计算机系统的第一处理器和外围环境之间进行数据交换的接口单元。 接口单元具有用于从外围环境接收输入数据的多个输入数据通道和第一访问管理单元。 访问管理单元被配置为从存储在接口单元中的第一接口处理器和存储在接口单元中的第二接口处理器接收提供存储在输入数据通道数量中的输入数据的请求，并且提供或 不将存储在输入数据通道中的输入数据提供给第一接口处理器和第二接口处理器。 第一优先级和第二优先级可以存储在第一访问管理单元中。
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公开(公告)号：US20150153413A1
公开(公告)日：2015-06-04
申请号：US14556830
申请日：2014-12-01
Inventor： Dirk HASSE , Peter SCHEIBELHUT , Robert POLNAU
IPC: G01R31/319 , G01R31/00
CPC classification number: G01R31/31917 , G01R31/005 , G06F11/26
Abstract: An apparatus for testing an electrical component, having a simulation unit for producing a simulation signal, a plurality of test units, and at least one electrical connecting device, whereby the simulation unit and the plurality of test units are connected or connectable to each other in an electrically conductive fashion via the at least one connecting device, and the at least one connecting device has at least one electrical switch device, which is situated to make or break an electrical connection between the plurality of test units.
Abstract translation: 一种用于测试电气部件的装置，具有用于产生模拟信号的模拟单元，多个测试单元和至少一个电连接装置，由此模拟单元和多个测试单元彼此连接或可连接 经由所述至少一个连接装置的导电方式，并且所述至少一个连接装置具有至少一个电气开关装置，所述至少一个电气开关装置被设置成使所述多个测试装置之间的电连接形成或断开。
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公开(公告)号：US20190165996A1
公开(公告)日：2019-05-30
申请号：US15822521
申请日：2017-11-27
Inventor： Matthias KLEMM , Heiko KALTE , Robert POLNAU , Thorsten BREHM , Jochen SAUER , Hans-Juergen MIKS , Robert LEINFELLNER , Ruediger KRAFT , Magnus ASPLUND , Matthias SCHMITZ
Abstract: A method for operating a real-time-capable simulation network having multiple network nodes for computing a simulation model. The network nodes are connected to one another via a serial data bus, and the network nodes exchange data via data bus messages. At least one event-driven task of the simulation model is implemented on a first network node, and a nondeterministic triggering event is detected by a second network node. The second network node communicates the detected triggering event to the first network node and the first network node computes the event-driven task. A fast response time is achieved by the means that a detection signal is sent from the second network node in the form of a multicast data bus message or a broadcast data bus message to multiple network nodes of the simulation network or to all network nodes of the simulation network over the serial data bus.
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公开(公告)号：US20140333344A1
公开(公告)日：2014-11-13
申请号：US14275284
申请日：2014-05-12
Inventor： Dirk HASSE , Robert POLNAU
IPC: H03K19/0175
CPC classification number: H03K19/017509 , G06F13/4291 , H03K19/0175 , H03K19/17732 , H03K19/17744
Abstract: A method for implementing an adaptive interface between at least one FPGA with at least one FPGA application and at least one I/O module, which are designed as the corresponding sender side or receiver side, for connection to the FPGA, whereby a serial interface is formed between the at least one FPGA and the at least one I/O module, comprising the steps of configuring a maximum number of registers to be transmitted for each FPGA application, configuring a shared, fixed register width for all registers, setting an enable signal on the sender side for the registers to be transmitted out of the maximum number of registers to be transmitted, transmitting the enable signal from the sender side to the receiver side, and transmitting the registers, for which the enable signal is set, from the sender side to the receiver side.
Abstract translation: 一种在至少一个FPGA与至少一个FPGA应用之间实现自适应接口的方法和被设计为相应的发送机侧或接收机侧的至少一个I / O模块，用于连接到FPGA，由此串行接口是 形成在所述至少一个FPGA和所述至少一个I / O模块之间，包括以下步骤：配置要针对每个FPGA应用发送的最大寄存器数量，为所有寄存器配置共享固定寄存器宽度，设置使能信号 在发送侧，要发送的寄存器的最大数量的寄存器发送，将发送端发送到接收端，并从发送方发送启用信号的寄存器 侧到接收机侧。
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