公开(公告)号：US20140324408A1

公开(公告)日：2014-10-30

申请号：US14055497

申请日：2013-10-16

Applicant: dSpace digital signal processing and control engineering GmbH

Inventor： Stefan MERTEN ,  Marc SCHLENGER ,  Holger ROSS ,  Frank MERTENS

IPC: G06F9/455

CPC classification number: G06F9/455 ,  G06F8/35 ,  G06F15/7871 ,  G06F17/5027 ,  G06F17/5054

Abstract: A method for generating software for a hardware component of a measuring, control, or regulating system having a processor, an FPGA, and a plurality of I/O channels. The I/O channels are connected to the FPGA and the FPGA is connected to the processor via a communications interface. The method includes the steps of selecting a first subset of the I/O channels for operation by the FPGA, generating a first application for execution in the FPGA, selecting a second subset of the I/O channels for operation by the processor, and generating a second application for execution on the processor. The step of generating a first application comprises generating code for connecting the second subset of I/O channels to the communications interface. The invention relates in addition to a method for operating a hardware component.

Abstract translation: 一种用于为具有处理器，FPGA和多个I / O通道的测量，控制或调节系统的硬件组件生成软件的方法。 I / O通道连接到FPGA，FPGA通过通信接口连接到处理器。 该方法包括以下步骤：选择由FPGA操作的I / O通道的第一子集，产生用于在FPGA中执行的第一应用，选择I / O通道的第二子集以供处理器操作，以及生成 用于在处理器上执行的第二应用程序。 生成第一应用的步骤包括生成用于将第二子I / O通道连接到通信接口的代码。 本发明除了用于操作硬件组件的方法之外还涉及。

公开(公告)号：US20210303501A1

公开(公告)日：2021-09-30

申请号：US17215967

申请日：2021-03-29

Applicant: dSPACE digital signal processing and control engineering GmbH

Inventor： Andreas AGNE ,  Dominik LUBELEY ,  Heiko KALTE ,  Marc SCHLENGER

IPC: G06F13/42

Abstract: To program a first programmable gate array, for example a first FPGA, in a distributed computer system, a configuration of a first configuration logic on the first programmable gate array is provided. The first configuration logic is configured to receive a first user bitstream from a configuration software for configuring a first user logic on the first programmable gate array and to store the first user bitstream on a non-volatile memory of the first programmable gate array for the purpose of subsequently configuring a first user logic on the first programmable gate array according to the specifications from the first user bitstream. In an expansion stage of the invention, a configuration of a programming logic on the first programmable gate array is also provided for programming a second programmable gate array, which is connected to the first programmable gate array to form a daisy chain.

公开(公告)号：US20170116363A1

公开(公告)日：2017-04-27

申请号：US15291113

申请日：2016-10-12

Applicant: dSPACE digital signal processing and control engineering GmbH

Inventor： Dominik LUBELEY ,  Marc SCHLENGER ,  Heiko KALTE

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F17/5022 ,  G06F17/5036 ,  G06F2217/78

Abstract: A method for determining the power consumption of a programmable logic device, in which at least one configuration parameter is determined in accordance with a predefined configuration and at least one device parameter is determined in accordance with the programmable logic device. The predefined configuration is designed such that the programmable logic device exchanges data with a computing unit through at least one interface pin and receives data from at least one signal source and/or sends it to at least one signal receiver through at least one interface pin. At least one data characteristic of the data exchanged between the computing unit and the programmable logic device as well as at least one signal characteristic of the data received from the at least one signal source and/or sent to the at least one signal receiver are determined.