公开(公告)号：US5410600A

公开(公告)日：1995-04-25

申请号：US795190

申请日：1991-11-18

申请人： James W. Toy

发明人： James W. Toy

IPC分类号： H04L25/03 ,  H04L9/00

CPC分类号： H04L25/03866

摘要： A prescramble encoding mechanism divides a data word into a plurality of sequences of data bits for transmission over a fiber optic communication link. Complementary versions of control bits and odd and even parity bits are interleaved between the bit parallel data and control signals, divides a parallel data word possible series of consecutive bits of the same logical state is less than a predetermined number related to the length of the data bit sequences and to placement of the complementary control bits and even and odd parity bits. The data frame is then scrambled prior to transmission over the fiber optic link. Depending on the exact nature of the scrambling and descrambling process, a single-bit link error may produce a plurality of bit errors in the descrambled frame. To increase the likelihood that the link error will be detected by the parity checks in the descrambled frame, a frame may be resequenced to separate adjacent bits prior to scrambling and resequenced back to the original sequence after descrambling. As a consequence, a single-bit link error which causes multiple descrambled bit errors will cause widely separated bit errors so that, for the most part, each error bit will be in a separate data bit sequence which is the subject of a separate parity bit calculation. At the receive end of the link, received signals are descrambled, resequenced back to their original order and then demultiplexed to respective outputs.

摘要翻译： 预编码编码机制将数据字划分成多个数据比特序列，以在光纤通信链路上传输。 控制位和奇偶校验位的互补版本在位并行数据和控制信号之间交错，将相同逻辑状态的并行数据字可能的连续位序列小于与数据长度相关的预定数量 位序列和互补控制位和偶校验位和奇校验位的放置。 然后在通过光纤链路传输之前将数据帧加扰。 取决于加扰和解扰过程的确切性质，单位链路错误可能在解扰帧中产生多个位错误。 为了增加通过解扰帧中的奇偶校验来检测到链路错误的可能性，可以对帧进行重排序，以在加扰之前分离相邻的比特，并在解扰后将其重新排序回原始序列。 因此，导致多个解扰比特错误的单比特链路错误将导致广泛分离的比特错误，使得大多数情况下，每个错误比特将处于单独的数据比特序列中，该比特序列是单独的奇偶校验位 计算。 在链路的接收端，接收到的信号被解扰，重新按照原先的顺序重新排序，然后解复用到各个输出端。

公开(公告)号：US5963608A

公开(公告)日：1999-10-05

申请号：US882923

申请日：1997-06-26

申请人： Paul W. Casper ,  Marc E. Sawyer

发明人： Paul W. Casper ,  Marc E. Sawyer

IPC分类号： H03L7/095 ,  H03L7/12 ,  H03L7/197 ,  H04L7/033 ,  H04L25/03 ,  H04L25/49 ,  H03D3/24

CPC分类号： H03L7/12 ,  H04L25/03866 ,  H04L25/4904 ,  H04L7/033 ,  H03L7/095 ,  H03L7/197

摘要： To derive a clock embedded in a digital data stream, a variable data rate synchronizer includes a data rate estimator that derives an estimate of the data rate of data contained in the digital data signal, and a frequency estimator that derives an estimate of the frequency of the output of a voltage controlled oscillator. A phase lock loop includes a phase detector to which the digital data signal and the output of the voltage controlled oscillator are coupled and has an output coupled to a sweepable loop filter. The output of the loop filter is coupled to the voltage controlled oscillator. During an initital frequency acquisition mode, the sweep controller sequentially varies an analog voltage applied to the voltage controlled oscillator, until the estimate of the data rate effectively corresponds to the estimate of the frequency of the output of the voltage controlled oscillator. This terminates the frequency acquisition mode and initiates a phase acquisition mode, during which the sweep controller causes a sawtooth sweep of the loop filter, until the output of the loop filter corresponds to the actual frequency of said embedded clock signal, thereby locking the loop to the embedded clock.

摘要翻译： 为了导出嵌入在数字数据流中的时钟，可变数据速率同步器包括导出数字数据信号中包含的数据的数据速率的估计的数据速率估计器，以及频率估计器， 压控振荡器的输出。 锁相环包括相位检测器，数字数据信号和压控振荡器的输出耦合到该相位检测器，并具有耦合到可扫描环路滤波器的输出。 环路滤波器的输出耦合到压控振荡器。 在初始频率获取模式期间，扫描控制器顺序地改变施加到压控振荡器的模拟电压，直到数据速率的估计对应于压控振荡器的输出频率的估计。 这终止了频率获取模式，并且启动相位采集模式，在此期间，扫描控制器引起环路滤波器的锯齿波扫描，直到环路滤波器的输出对应于所述嵌入式时钟信号的实际频率，由此锁定环路 嵌入式时钟。

公开(公告)号：US5838749A

公开(公告)日：1998-11-17

申请号：US462168

申请日：1995-06-05

申请人： Paul W. Casper ,  Jeffrey S. Grant ,  Marc E. Sawyer

发明人： Paul W. Casper ,  Jeffrey S. Grant ,  Marc E. Sawyer

IPC分类号： H03L7/095 ,  H03L7/12 ,  H03L7/197 ,  H04L7/033 ,  H04L25/03 ,  H04L25/49 ,  H04L7/00

CPC分类号： H04L7/033 ,  H03L7/12 ,  H04L25/03866 ,  H04L25/4904 ,  H03L7/095 ,  H03L7/197

摘要： A data and clock recovery arrangement, for a high speed fiber optic digital communication system in which a serial digital bit stream is pre-scramble encoded by interleaving complementary pairs of overhead bits between successive groups of data bits, and then scrambled and transmitted to a receive site, comprises a data rate independent variable bit rate synchronizer, a descrambler and a decoder. The data rate independent variable bit synchronizer processes the received scrambled and encoded digital bit stream to derive a variable data rate synchronization clock signal. The synchronizer is capable of accepting any data rate within the operational data clock signal range of the system, and automatically tunes itself to the data clock signal embedded in the received scrambled and encoded serial data stream, so as to output respective scrambled and encoded serial data and clock signals. The descrambler descrambles the scrambled and encoded serial digital bit stream using the variable data rate synchronization clock signal, and the decoder decodes the descrambled serial digital bit stream to extract groups of data bits exclusive of the complementary pairs of overhead bits and to derive an output clock signal having a frequency coincident with the data rate of the data bits.

摘要翻译： 一种用于高速光纤数字通信系统的数据和时钟恢复装置，其中串行数字比特流通过在连续的数据比特组之间交织开销比特的互补对进行加密编码，然后被加扰并发送到接收 包括数据速率独立的可变比特率同步器，解扰器和解码器。 数据速率独立的可变位同步器处理接收的加密和编码的数字比特流以导出可变数据速率同步时钟信号。 同步器能够接受系统的运行数据时钟信号范围内的任何数据速率，并自动调谐到嵌入在接收的经加扰和编码的串行数据流中的数据时钟信号，以输出相应的加扰和编码串行数据 和时钟信号。 解扰器使用可变数据速率同步时钟信号对加扰和编码的串行数字比特流进行解扰，并且解码器解码解扰的串行数字比特流以提取不同于开销比特的互补对的数据比特组，并且导出输出时钟 信号具有与数据位的数据速率一致的频率。

公开(公告)号：US5754577A

公开(公告)日：1998-05-19

申请号：US685440

申请日：1996-07-23

申请人： Paul W. Casper ,  Arthur Gerard Wilson

发明人： Paul W. Casper ,  Arthur Gerard Wilson

IPC分类号： H01S5/0683 ,  H01S3/103

CPC分类号： H01S5/0683 ,  H01S5/06832

摘要： A modulation drive current control loop for a digitally modulated laser diode uses the small signal, square-law portion of an RF signal diode detection circuit to adjust the magnitude of laser modulation drive current, and compensate for variations in temperature and aging of the laser diode. Operating the RF signal detector diode as a non-switched device, in its square-law region, provides several advantages over large signal, switched, linear region devices. When a detector diode is operated in the large signal, switched, linear region, its output depends upon the reduced slope beyond the `knee` region of the curve, so that the diode functions essentially as a switch. In such a large signal detection mode, the diode conducts during only a portion of the input cycle, with its output voltage following peaks of the input signal waveform in accordance with a linear relationship between input voltage and output voltage. This requirement for both a large valued input signal (to overcome the bandgap voltage of the diode) and the need to switch the detector diode on and off necessarily prevents its use with precision at very high (e.g., gigabit) data rates. In contrast therewith, the small signal, square-low detector diode of the present invention can easily produce a proportional output voltage at gigabit speeds using a very small amplitude input signal.

摘要翻译： 用于数字调制的激光二极管的调制驱动电流控制环路使用RF信号二极管检测电路的小信号，平方律部分来调整激光调制驱动电流的大小，并补偿激光二极管的温度和老化的变化 。 在其平方律区域中操作RF信号检测器二极管作为非开关器件，与大信号，开关，线性区域器件相比提供了几个优点。 当检测器二极管在大信号切换的线性区域中工作时，其输出取决于曲线的“拐点”区域之后的斜率减小，因此二极管基本上起着开关的作用。 在这样大的信号检测模式下，二极管仅在输入周期的一部分期间导通，其输出电压按照输入电压和输出电压之间的线性关系跟随输入信号波形的峰值。 对于大值输入信号（克服二极管的带隙电压）和需要将检测器二极管打开和关闭的需要，必须防止在非常高（例如千兆位）数据速率下的精确使用。 相比之下，本发明的小信号，方形低检测器二极管可以使用非常小的振幅输入信号容易地以千兆位速度产生比例输出电压。