-
公开(公告)号：US20170194973A1
公开(公告)日：2017-07-06
申请号：US15377917
申请日：2016-12-13
申请人： NXP B.V.
发明人： Ulrich Moehlmann
CPC分类号： H03L7/0991 , G01S7/35 , H03L7/093 , H03L7/099 , H03L7/12 , H03L2207/06 , H03L2207/50
摘要： An all digital phase locked loop system for tracking a variable frequency input signal and method of operation are described. The ADPLL system includes a digital phase locked loop, including a digitally controlled oscillator, and a model of the digitally controller oscillator. The model represents the behaviour of the digitally controlled oscillator as a function of frequency and has a model input arranged to receive a signal indicating a current target frequency. The model is configured to output at least one control signal to control the frequency of the digitally controlled oscillator to be closer to the current target frequency. The digital phase locked loop is configured to control the digitally controlled oscillator to reduce any difference between the frequency of the digitally controlled oscillator and the current target frequency arising from any deviation of the model of the digitally controlled oscillator from the digitally controlled oscillator.
-
2.发明授权Phase lock loop with tracking filter for attenuating spurious signals of a swept local oscillator 有权具有跟踪滤波器的锁相环，用于衰减扫频本地振荡器的杂散信号公开(公告)号：US09083351B1
公开(公告)日：2015-07-14
申请号：US13794329
申请日：2013-03-11
申请人： Raytheon Company
CPC分类号： H03L7/12 , H01P1/20 , H03L7/0812 , H03L7/093
摘要： A high spectral purity swept local oscillator including a tracking filter. The output of a swept DDS oscillator may be improved by filtering it with a band-pass filter having an adjustable center frequency, which is adjusted in real time to track the instantaneous frequency of the DDS oscillator. The tracking may be accomplished by comparing, using a phase comparator, the phase at the output of the band-pass filter to the phase at its input, and feeding back to the frequency control input of the band-pass filter a signal corresponding to the phase difference measured by the phase comparator.
摘要翻译： 包括跟踪滤波器的高频纯度扫频本地振荡器。 扫描DDS振荡器的输出可以通过用具有可调节的中心频率的带通滤波器进行滤波来提高，该滤波器可以实时调整以跟踪DDS振荡器的瞬时频率。 可以通过使用相位比较器将带通滤波器的输出端的相位与其输入端的相位进行比较，并将带通滤波器的频率控制输入反馈到与 由相位比较器测量的相位差。
-
公开(公告)号：US08981855B2
公开(公告)日：2015-03-17
申请号：US13854498
申请日：2013-04-01
发明人： Luca Romano , Randy Tsang
CPC分类号： H03L7/099 , H03J2200/10 , H03L7/085 , H03L7/103 , H03L7/12 , H03L2207/06
摘要： Aspects of the disclosure provide a phase-locked loop (PLL). The PLL includes a voltage-controlled oscillator (VCO), a detector module, and a ramp module. The VCO has a first capacitor unit and a second capacitor unit. The VCO is configured to generate an oscillating signal having a frequency based on a first capacitance of the first capacitor unit and a second capacitance of the second capacitor unit. The detector module is configured to generate a voltage signal as a function of the oscillating signal and a reference signal. The voltage signal is used to control the first capacitor unit to stabilize the frequency of the oscillating signal. The ramp module is configured to generate a ramp signal based on the voltage signal. The ramp signal is used to control the second capacitor unit to ramp the second capacitance from a first value to a second value.
摘要翻译： 本公开的方面提供了锁相环（PLL）。 PLL包括压控振荡器（VCO），检测器模块和斜坡模块。 VCO具有第一电容器单元和第二电容器单元。 VCO被配置为产生具有基于第一电容器单元的第一电容的频率和第二电容器单元的第二电容的振荡信号。 检测器模块被配置为产生作为振荡信号和参考信号的函数的电压信号。 电压信号用于控制第一电容器单元以稳定振荡信号的频率。 斜坡模块被配置为基于电压信号产生斜坡信号。 斜坡信号用于控制第二电容器单元以将第二电容从第一值斜坡化为第二值。
-
公开(公告)号：US08884705B2
公开(公告)日：2014-11-11
申请号：US13582808
申请日：2011-03-03
申请人： Emeric De Foucauld
发明人： Emeric De Foucauld
摘要： A frequency synthesis device with a feedback loop includes: a phase-comparison control circuit; a frequency conversion unit voltage controlled by the control circuit; a feedback loop for supplying at least one signal issuing from the frequency conversion unit to the control circuit; at least one other control circuit for voltage control of the frequency conversion unit; and at least one other feedback loop for supplying at least one other signal issuing from the frequency conversion unit to the other control circuit.
摘要翻译： 具有反馈回路的频率合成装置包括：相位比较控制电路; 由控制电路控制的变频单元电压; 反馈回路，用于将从变频单元发出的至少一个信号提供给控制电路; 至少一个用于所述变频单元的电压控制的控制电路; 以及至少一个其他反馈回路，用于将从频率转换单元发出的至少一个其它信号提供给另一个控制电路。
-
公开(公告)号：US08030984B2
公开(公告)日：2011-10-04
申请号：US12514617
申请日：2007-11-13
申请人： Michel Ayraud
发明人： Michel Ayraud
CPC分类号： H04L7/033 , H03L7/091 , H03L7/093 , H03L7/12 , H04L7/0087
摘要： The invention relates to an electronic circuit making it possible to extract a clock signal from an incident binary data sequence arriving at a constant rate. The electronic circuit comprises an oscillator (VCO) with voltage-controlled frequency providing a sinusoidal signal, a circuit (R, Cp, RD, I1, I2) for extracting the transition edges of the binary sequence producing a brief pulse at each transition, a sampler (MLT) for tapping off the level of the sinusoidal voltage at the instant of the brief pulse, and an integrator (AOP, R1, C1) for integrating this level in tandem with the successive pulses, the output of the integrator being applied as control voltage to the oscillator with controlled frequency, the output of the oscillator being the desired clock frequency with a slaved phase passing through zero substantially in the middle of the interval between two binary data transitions. Such a circuit is useful in applications for transmitting digital data of serial type, in which the data are received without at the same time receiving a clock signal.
摘要翻译： 本发明涉及一种电子电路，使得可以从以恒定速率到达的入射二进制数据序列中提取时钟信号。 电子电路包括具有提供正弦信号的压控频率的振荡器（VCO），用于提取二进制序列的过渡边沿的电路（R，Cp，RD，I1，I2），以产生每个转换时的短脉冲， 采样器（MLT），用于在短脉冲时刻点击正弦电压的电平;以及积分器（AOP，R1，C1），用于将该电平与连续脉冲串联，积分器的输出作为 控制电压到具有受控频率的振荡器，振荡器的输出是期望的时钟频率，其中从动相位基本上在两个二进制数据转换之间的间隔的中间通过零。 这种电路在用于发送串行类型的数字数据的应用中是有用的，其中接收数据而不同时接收时钟信号。
-
公开(公告)号：US20100194483A1
公开(公告)日：2010-08-05
申请号：US12365921
申请日：2009-02-05
IPC分类号： H03L7/00
CPC分类号： H03L7/10 , H03L7/0995 , H03L7/12 , H03L7/187 , H03L2207/06
摘要： A phase locked loop (“PLL”) includes a voltage controlled oscillator (“VCO”) operable to acquire and maintain lock at a selected output frequency of the VCO and control logic operable to perform steps in a method of selecting a frequency band for operating the VCO. Such method can include switching the VCO to a given operating band from among the plurality of operating bands of the VCO; determining a band center frequency at which the VCO oscillates in the given operating band when the control voltage is set to a center of a range of minimum to maximum control voltages [CVmin, CVmax]; determining a difference between the band center frequency and the selected output frequency when the selected output frequency is within the given operating band; switching the VCO to another operating band; repeating the above steps until a difference between the band center frequency and the selected output frequency increases; and selecting the operating band for operation of the VCO for which the difference between the band center frequency and the selected output frequency is smallest.
摘要翻译： 锁相环（“PLL”）包括压控振荡器（“VCO”），其可操作以获取并维持VCO的所选输出频率处的锁定和可操作以执行选择用于操作的频带的方法中的步骤的步骤 VCO。 这种方法可以包括将VCO切换到来自VCO的多个工作频带中的给定工作频带; 当控制电压被设置为最小到最大控制电压[CVmin，CVmax]的范围的中心时，确定VCO在给定工作频带中振荡的频带中心频率; 当所选择的输出频率在所述给定的工作频带内时，确定所述频带中心频率与所选择的输出频率之间的差; 将VCO切换到另一个工作频带; 重复上述步骤，直到频带中心频率和所选择的输出频率之间的差异增加; 以及选择用于频带中心频率和所选输出频率之间的差最小的VCO的工作频带。
-
公开(公告)号：US20100013520A1
公开(公告)日：2010-01-21
申请号：US12514617
申请日：2007-11-13
申请人： Michel Ayraud
发明人： Michel Ayraud
IPC分类号： H04L7/033
CPC分类号： H04L7/033 , H03L7/091 , H03L7/093 , H03L7/12 , H04L7/0087
摘要： The invention relates to an electronic circuit making it possible to extract a clock signal from an incident binary data sequence arriving at a constant rate. The electronic circuit comprises an oscillator (VCO) with voltage-controlled frequency providing a sinusoidal signal, a circuit (R, Cp, RD, I1, I2) for extracting the transition edges of the binary sequence producing a brief pulse at each transition, a sampler (MLT) for tapping off the level of the sinusoidal voltage at the instant of the brief pulse, and an integrator (AOP, R1, C1) for integrating this level in tandem with the successive pulses, the output of the integrator being applied as control voltage to the oscillator with controlled frequency, the output of the oscillator being the desired clock frequency with a slaved phase passing through zero substantially in the middle of the interval between two binary data transitions. Such a circuit is useful in applications for transmitting digital data of serial type, in which the data are received without at the same time receiving a clock signal.
摘要翻译： 本发明涉及一种电子电路，使得可以从以恒定速率到达的入射二进制数据序列中提取时钟信号。 电子电路包括具有提供正弦信号的压控频率的振荡器（VCO），用于提取二进制序列的过渡边沿的电路（R，Cp，RD，I1，I2），以产生每个转换时的短脉冲， 采样器（MLT），用于在短脉冲时刻点击正弦电压的电平;以及积分器（AOP，R1，C1），用于将该电平与连续脉冲串联，积分器的输出作为 控制电压到具有受控频率的振荡器，振荡器的输出是期望的时钟频率，其中从动相位基本上在两个二进制数据转换之间的间隔的中间通过零。 这种电路在用于发送串行类型的数字数据的应用中是有用的，其中接收数据而不同时接收时钟信号。
-
公开(公告)号：US07346133B2
公开(公告)日：2008-03-18
申请号：US10772441
申请日：2004-02-06
申请人： James E. Tatem, Jr.
发明人： James E. Tatem, Jr.
CPC分类号： A61B17/320016 , A61B17/3207 , A61B2017/320741 , A61B2090/033 , H03J7/04 , H03J7/065 , H03J7/22 , H03J7/285 , H03L7/07 , H03L7/0805 , H03L7/12 , H04L7/033 , H04L7/04
摘要： Systems and methods for providing frequency compensation over a wide range of frequency drift are shown. The preferred embodiment utilizes a sweep mode function to provide frequency compensation over a range of frequency drift broader than the frequency drift accommodated by a phase lock loop, without increasing the noise characteristics of the phase lock loop. Accordingly, the preferred embodiment operates in a phase lock loop mode while frequency drift can be compensated for by the lock range of the phase lock loop circuitry. The preferred embodiment operates in sweep mode to step through a range of offset frequencies to position the phase lock loop mode where frequency drift can be compensated for by the lock range of phase lock loop circuitry. Additionally, a preferred embodiment of the present invention includes a drift mode in order to monitor frequency offset information, such as may be used in performing sweep mode functions and/or other control or management functions.
摘要翻译： 示出了在宽频率漂移范围内提供频率补偿的系统和方法。 优选实施例利用扫描模式功能来在比锁相环容纳的频率漂移更宽的频率范围内提供频率补偿，而不增加锁相环的噪声特性。 因此，优选实施例在锁相环模式下工作，同时可以通过锁相环电路的锁定范围补偿频率漂移。 优选实施例以扫描模式操作以跨越偏移频率的范围来定位锁相环模式，其中通过锁相环电路的锁定范围可以补偿频率漂移。 此外，本发明的优选实施例包括漂移模式以便监视频率偏移信息，诸如可用于执行扫描模式功能和/或其他控制或管理功能。
-
公开(公告)号：US20060244542A1
公开(公告)日：2006-11-02
申请号：US11476690
申请日：2006-06-29
申请人： Ernest Knoll , Eyal Fayneh
发明人： Ernest Knoll , Eyal Fayneh
IPC分类号： H03L7/00
CPC分类号： H03L7/10 , H03L7/0893 , H03L7/12 , H03L7/18
摘要： An apparatus for controlling a phase-locked loop includes a detector for detecting at least one of a startup condition and a yank condition and a controller for controlling current between a charge pump and the phase-locked loop. If a startup condition is detected, the controller sinks current from a control node connected to a loop filter of the phase-locked loop. This, in turn, causes a bias voltage to increase until the phase-locked loop transitions from startup mode to a normal acquisition mode. The current sink is provided by a dummy charge pump and the startup condition is determined by detecting the end of a PLL disable state. If a yank condition is detected, a charge pump connected to a phase-frequency detector of the phase-locked loop controls the bias voltage until a feedback frequency becomes lower than a reference frequency. Methods for controlling a phase-locked loop during both modes of operation may use of the aforementioned apparatus.
摘要翻译： 用于控制锁相环的装置包括用于检测启动条件和绞盘状况中的至少一个的检测器和用于控制电荷泵和锁相环之间的电流的控制器。 如果检测到启动条件，则控制器从连接到锁相环的环路滤波器的控制节点吸收电流。 这反过来导致偏置电压增加，直到锁相环从启动模式转换到正常采集模式。 电流吸收器由虚拟电荷泵提供，并且通过检测PLL禁止状态的结束来确定启动条件。 如果检测到牦牛病情，则连接到锁相环的相位频率检测器的电荷泵控制偏置电压，直到反馈频率变得低于参考频率。 在两种操作模式下控制锁相环的方法可以使用上述装置。
-
公开(公告)号：US06823031B1
公开(公告)日：2004-11-23
申请号：US09488313
申请日：2000-01-20
申请人： James E. Tatem, Jr.
发明人： James E. Tatem, Jr.
IPC分类号： H03D324
CPC分类号： A61B17/320016 , A61B17/3207 , A61B2017/320741 , A61B2090/033 , H03J7/04 , H03J7/065 , H03J7/22 , H03J7/285 , H03L7/07 , H03L7/0805 , H03L7/12 , H04L7/033 , H04L7/04
摘要： Systems and methods for providing frequency compensation over a wide range of frequency drift are shown. The preferred embodiment utilizes a sweep mode function to provide frequency compensation over a range of frequency drift broader than the frequency drift accommodated by a phase lock loop, without increasing the noise characteristics of the phase lock loop. Accordingly, the preferred embodiment operates in a phase lock loop mode while frequency drift can be compensated for by the lock range of the phase lock loop circuitry. The preferred embodiment operates in sweep mode to step through a range of offset frequencies to position the phase lock loop mode where frequency drift can be compensated for by the lock range of phase lock loop circuitry. Additionally, a preferred embodiment of the present invention includes a drift mode in order to monitor frequency offset information, such as may be used in performing sweep mode functions and/or other control or management functions.
-
-
-
-
-
-
-
-
-
搜索结果
178 条记录 (耗时 0.021 秒)
