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公开(公告)号：US07078304B2
公开(公告)日：2006-07-18
申请号：US11098738
申请日：2005-04-04
IPC分类号： H01L21/8222
CPC分类号： H05K1/186 , G06K19/07749 , H01L23/49833 , H01L2224/16 , H05K1/189 , H05K2201/055
摘要： An electrical circuit is formed by forming and patterning a conductive layer on a substrate, forming and patterning a conductive layer on another substrate, depositing a dielectric layer on at least a portion of one of conductive layers, mounting an integrated circuit (IC) between the substrates, coupling the IC to the conductive layers, and affixing the substrates together with the conductive layers between the substrates. These are either separate substrates or a unitary substrate. The IC is mounted either to a substrate, a conductive layer, or a dielectric layer. The IC is coupled to the conductive layers either directly or through openings formed in the dielectric layer. An interior conductive layer may be used to couple the IC to the conductive layers.
摘要翻译： 通过在衬底上形成和图案化导电层形成电路，在另一个衬底上形成和构图导电层，在导电层的至少一部分上沉积介电层，将集成电路（IC）安装在 衬底，将IC耦合到导电层，以及将衬底与导电层粘合在衬底之间。 这些是单独的基底或单一基底。 IC安装在基板，导电层或电介质层上。 IC直接地或通过形成在电介质层中的开口耦合到导电层。 内部导电层可以用于将IC耦合到导电层。
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公开(公告)号：US07542315B2
公开(公告)日：2009-06-02
申请号：US11564932
申请日：2006-11-30
申请人： Alan D. DeVilbiss
发明人： Alan D. DeVilbiss
CPC分类号： H02M7/217
摘要： A voltage signal rectifier produces a rectified voltage signal from an input offset voltage signal. The voltage signal rectifier includes input offset, output, and reference nodes, two actively controlled current regulation elements (ACCREs), and two controllers. The input offset node is coupled to the input offset voltage signal. The rectified voltage signal is generated onto the output node. The reference node is coupled to a reference voltage for the input offset and rectified voltage signals. The ACCREs are coupled to the input offset node and one of the ACCREs is coupled to the output node. Each controller is configured to control the one of the ACCREs so that the ACCRE coupled to the output node allows current flow through it when the input offset voltage signal is higher than the rectified voltage signal and the other ACCRE is configured to allows current flow through it when the input offset voltage signal is lower than the rectified voltage signal.
摘要翻译： 电压信号整流器从输入偏移电压信号产生整流电压信号。 电压信号整流器包括输入偏移，输出和参考节点，两个主动控制的电流调节元件（ACCRE）和两个控制器。 输入偏移节点耦合到输入偏移电压信号。 整流电压信号被产生到输出节点上。 参考节点耦合到用于输入偏移和整流电压信号的参考电压。 ACCRE耦合到输入偏移节点，并且ACCRE中的一个耦合到输出节点。 每个控制器被配置为控制ACCRE中的一个，使得当输入偏移电压信号高于整流电压信号时，耦合到输出节点的ACCRE允许电流流过它，而另一个ACCRE被配置为允许电流流过它 当输入失调电压信号低于整流电压信号时。
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公开(公告)号：US06031754A
公开(公告)日：2000-02-29
申请号：US184474
申请日：1998-11-02
CPC分类号： G11C11/22
摘要： A ferroelectric integrated circuit memory includes a memory cell having a ferroelectric capacitor, one electrode of which is connected to a bit line through a transistor, and the other electrode of which is connected to a plate line. The bit line is also connected to system ground through a precharge transistor. In a read cycle, the precharge transistor remains on after the word line goes high connecting the capacitor to the bit line. At least a portion of the linear displacement current that flows to the bit line is drained off to ground via the precharge transistor, thereby increasing the switching voltage across the ferroelectric capacitor. The precharge transistor is turned off before or during the switching of the ferroelectric capacitor. The signal applied to the gate of the precharge transistor is boosted above the supply voltage of the memory to shorten the cycle time.
摘要翻译： 铁电集成电路存储器包括具有铁电电容器的存储单元，其一个电极通过晶体管连接到位线，并且另一个电极连接到板线。 位线也通过预充电晶体管连接到系统地。 在读周期中，在字线连接电容器到位线之后，预充电晶体管保持导通。 流过位线的线性位移电流的至少一部分经由预充电晶体管被排出到地，从而增加了铁电电容器两端的开关电压。 预充电晶体管在铁电电容器的切换之前或期间被关断。 施加到预充电晶体管的栅极的信号被提升到高于存储器的电源电压以缩短周期时间。
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公开(公告)号：US20180025766A1
公开(公告)日：2018-01-25
申请号：US15218336
申请日：2016-07-25
IPC分类号： G11C11/22
摘要： An integrated circuit memory contains a memory cell connected to a bit line that does not float during a portion or all of the read sensing part of the read cycle. The memory cell includes a data storage device. The data storage device may be a ferroelectric capacitor, a linear capacitor, a floating gate transistor, a magnetic device, a resistive device or other type of data storage device capable of placing a charge on the bit line corresponding to a specific data state of the memory cell. The bit line and a reference bit line are connected to a differential amplifier and precharged to specified voltages. Preferably, a self-nulling sense amplifier circuit is connected to the bit lines that compensates for sense amplifier offset by applying additional charges on the bit lines. Alternatively, charge sources may be connected to the bit lines to provide additional charges on the bit lines during the read cycle. Memory cells according to this invention can be configured to provide a reference cell for the reference bit line.
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公开(公告)号：US06900536B1
公开(公告)日：2005-05-31
申请号：US10132939
申请日：2002-04-26
IPC分类号： G06K19/077 , H01L20060101 , H01L21/44 , H01L23/34 , H01L23/498 , H05K1/18 , H05K5/00
CPC分类号： H05K1/186 , G06K19/07749 , H01L23/49833 , H01L2224/16 , H05K1/189 , H05K2201/055
摘要： An electrical circuit is formed by forming and patterning a conductive layer on a substrate, forming and patterning a conductive layer on another substrate, depositing a dielectric layer on at least a portion of one of conductive layers, mounting an integrated circuit (IC) between the substrates, coupling the IC to the conductive layers, and affixing the substrates together with the conductive layers between the substrates. These are either separate substrates or a unitary substrate. The IC is mounted either to a substrate, a conductive layer, or a dielectric layer. The IC is coupled to the conductive layers either directly or through openings formed in the dielectric layer. An interior conductive layer may be used to couple the IC to the conductive layers.
摘要翻译： 通过在衬底上形成和图案化导电层形成电路，在另一个衬底上形成和构图导电层，在导电层之一的至少一部分上沉积介电层，将集成电路（IC）安装在 衬底，将IC耦合到导电层，以及将衬底与导电层粘合在衬底之间。 这些是单独的基底或单一基底。 IC安装在基板，导电层或电介质层上。 IC直接地或通过形成在电介质层中的开口耦合到导电层。 内部导电层可以用于将IC耦合到导电层。
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6.发明授权Ferroelectric memory with two ferroelectric capacitors in memory cell and method of operating same 失效铁电存储器与存储单元中的两个铁电电容器及其操作方法相同
公开(公告)号：US6147895A
公开(公告)日：2000-11-14
申请号：US326413
申请日：1999-06-04
申请人： David A. Kamp
发明人： David A. Kamp
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A ferroelectric integrated circuit memory includes a memory cell having a first ferroelectric capacitor, one electrode of which is connected to a first bit line through a first transistor and the other electrode of which is connected to a plate line; and a second ferroelectric capacitor, one electrode of which is connected to a second bit line through a second transistor and the other electrode of which is connected to the plate line. The plate line is parallel to the bit lines. The plate line is at 1/2 Vdd. The cell is written to by driving both bit lines either to Vdd or zero volts. The cell is read by driving one bit line to Vdd and the other to zero volts, and sensing the voltage change on the plate line. A shunt system holds the isolated node to the same voltage as the plate line when the row is not selected, thus providing a ferroelectric memory architecture that is unaffected by changes, such as aging, in the ferroelectric material, and has no disturb voltages.
摘要翻译： 铁电集成电路存储器包括具有第一铁电电容器的存储单元，其一个电极通过第一晶体管连接到第一位线，而另一个电极连接到板极线; 以及第二铁电电容器，其一个电极通过第二晶体管连接到第二位线，并且另一个电极连接到板极线。 平板线与位线平行。 板线为+ E，fra 1/2 + EE Vdd。 通过将两条位线驱动到Vdd或零伏来将单元写入。 通过将一个位线驱动到Vdd并将另一个位线驱动到零伏特来读取单元，并感测板极线上的电压变化。 当不选择该行时，分流系统将隔离节点保持与板线相同的电压，从而提供不受铁电材料中的老化等变化影响的铁电存储器架构，并且没有干扰电压。
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公开(公告)号：US5995407A
公开(公告)日：1999-11-30
申请号：US170418
申请日：1998-10-13
申请人： David A. Kamp
发明人： David A. Kamp
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A ferroelectric integrated circuit memory includes a memory cell having a ferroelectric capacitor, one electrode of which is connected to a bit line through a transistor and the other electrode of which is connected to a plate line. The plate line is floating at one-half Vcc when the bit line is lowered to zero volts to develop a read voltage on the plate line. A unity gain amplifierthen drives a complementary plate line to the same voltage as the plate line, then the plate line and complementary plate line are connected via a transistor, and the bit line is raised to Vcc to develop a reference voltage. This operation subtracts the read voltage from the reference voltage to develop a net voltage on the complementary plate line. The voltage on the complementary plate line is applied to the output line, compared via a sense amplifier to a one-half Vcc voltage on the input line, and the sense amp then drives the input and output lines to zero and Vcc, depending on whether the developed voltage was greater or less than one-half Vcc.
摘要翻译： 铁电集成电路存储器包括具有铁电电容器的存储单元，其一个电极通过晶体管连接到位线，并且另一个电极连接到板线。 当位线降低到零伏特时，板线浮动在一半Vcc，以在板线上产生读取电压。 单位增益放大器将互补板线驱动到与板线相同的电压，然后板线和互补板线通过晶体管连接，并将位线升高到Vcc以产生参考电压。 该操作从参考电压中减去读取电压，以在互补板线上产生净电压。 互补板线上的电压被施加到输出线，通过读出放大器与输入线上的一半Vcc电压进行比较，然后感测放大器将输入和输出线驱动到零和Vcc，取决于是否 开发的电压大于或小于半Vcc。
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8.发明授权Ferroelectric memory cell with shunted ferroelectric capacitor and method of making same 失效具有分流铁电电容器的铁电存储器及其制造方法
公开(公告)号：US5959878A
公开(公告)日：1999-09-28
申请号：US931023
申请日：1997-09-15
申请人： David A. Kamp
发明人： David A. Kamp
IPC分类号： G11C11/22 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L27/115 , G11C13/00
CPC分类号： H01L27/11502 , G11C11/22
摘要： A ferroelectric memory includes a transistor having a source/drain, a capacitor having a first electrode and a second electrode, and a plate line connected to the second electrode. The first electrode is connected to the source/drain of the transistor to create a node that is isolated when the transistor is off. A shunt system directly electrically connects the isolated node and the second electrode of said capacitor at a predetermined time to essentially equalize the voltages on the first and second electrodes of said capacitor during the predetermined time. In different embodiments the shunt is a Schottky diode, a resistor, and a pair of back-to-back diodes and a transistor. In the embodiment in which the shunt is a transistor, the shunt line connected to the shunt transistor gate is boosted, there is a shunt transistor connecting each isolated node in a portion of the memory, to the adjacent isolated node, and every eight to thirty-two isolated nodes, another shunt transistor connects the chain of isolated nodes to the plate line.
摘要翻译： 铁电存储器包括具有源极/漏极的晶体管，具有第一电极和第二电极的电容器，以及连接到第二电极的板极线。 第一电极连接到晶体管的源极/漏极，以产生当晶体管截止时被隔离的节点。 分流系统在预定时间内直接电连接所述电容器的隔离节点和第二电极，以在预定时间内基本上均衡所述电容器的第一和第二电极上的电压。 在不同的实施例中，并联是肖特基二极管，电阻器和一对背对背二极管和晶体管。 在分流器是晶体管的实施例中，连接到并联晶体管栅极的分流线被升压，存在将存储器的一部分中的每个隔离节点连接到相邻的隔离节点的并联晶体管，并且每八到三十 - 两个隔离节点，另一个分流晶体管将隔离节点链连接到板线。
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公开(公告)号：US10998030B2
公开(公告)日：2021-05-04
申请号：US15218336
申请日：2016-07-25
IPC分类号： G11C11/22
摘要： An integrated circuit memory contains a memory cell connected to a bit line that does not float during a portion or all of the read sensing part of the read cycle. The memory cell includes a data storage device. The data storage device may be a ferroelectric capacitor, a linear capacitor, a floating gate transistor, a magnetic device, a resistive device or other type of data storage device capable of placing a charge on the bit line corresponding to a specific data state of the memory cell. The bit line and a reference bit line are connected to a differential amplifier and precharged to specified voltages. Preferably, a self-nulling sense amplifier circuit is connected to the bit lines that compensates for sense amplifier offset by applying additional charges on the bit lines. Alternatively, charge sources may be connected to the bit lines to provide additional charges on the bit lines during the read cycle. Memory cells according to this invention can be configured to provide a reference cell for the reference bit line.
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