公开(公告)号：US08115564B2

公开(公告)日：2012-02-14

申请号：US12839635

申请日：2010-07-20

申请人： Michael A. Kost

发明人： Michael A. Kost

IPC分类号： H03K7/08

CPC分类号： H03K7/08 ,  H03F1/305 ,  H03F3/2171 ,  H03K5/1515

摘要： Systems and methods for minimizing startup transients in digital audio controllers that may result in audible artifacts in the output of an audio amplification system. One embodiment comprises a digital PWM amplifier that includes a mechanism for controlling the amount of dead time in the audio output signal. When the amplifier starts up, the PWM signals provided to the output stage are simultaneously deasserted (i.e., there is dead time) for most of each switch period. The amount of dead time is gradually reduced over a series of switch periods until a nominal operating amount of dead time in each switch period is reached. Thus, the PWM signals are slowly ramped up from having a very large percentage of dead time (e.g., nearly 100%) to having a very small percentage of dead time (e.g., 1-2% to prevent shoot-through.)

摘要翻译： 用于最小化数字音频控制器中的启动瞬变的系统和方法，其可能导致音频放大系统的输出中的可听见的伪影。 一个实施例包括数字PWM放大器，其包括用于控制音频输出信号中的死区时间量的机构。 当放大器启动时，提供给输出级的PWM信号在每个开关周期的大部分时间同时被断言（即，存在死区时间）。 在一系列开关周期内死区时间逐渐减少，直到达到每个开关周期内的死区时间的标称操作量。 因此，PWM信号从死区时间的很大百分比（例如近100％）缓慢上升到具有非常小百分比的死区时间（例如，1-2％以防止直通）。

公开(公告)号：US07738613B1

公开(公告)日：2010-06-15

申请号：US10805574

申请日：2004-03-20

申请人： Jack B. Andersen ,  Joel W. Page ,  Daniel L. W. Chieng ,  Douglas D. Gephardt

发明人： Jack B. Andersen ,  Joel W. Page ,  Daniel L. W. Chieng ,  Douglas D. Gephardt

IPC分类号： H04L7/00

CPC分类号： H04L7/0029 ,  H03H17/0275 ,  H03H17/0685 ,  H04L7/005 ,  H04L25/4902

摘要： Systems and methods for converting a data stream from a first sample rate to a second sample rate, where the data is received in bursts. In one embodiment, a method includes receiving bursty audio data on a first input line and receiving synchronization data on a second input line that is separate from the first input line. An input sample rate is then estimated for the received audio data based on the received synchronization data and the audio data is converted to an output sample rate. The input sample rate is determined by counting samples received in a time interval and potentially low-pass filtering the result. The audio data may be in packetized, parallel, or other forms, and the synchronization data may include individual signals, such as pulses or bits received at regular or irregular intervals.

摘要翻译： 用于将数据流从第一采样率转换为第二采样率的系统和方法，其中数据以突发方式接收。 在一个实施例中，一种方法包括在第一输入线上接收突发音频数据，并在与第一输入线分开的第二输入线上接收同步数据。 然后，基于接收到的同步数据对接收到的音频数据估计输入采样率，并将音频数据转换为输出采样率。 输入采样率通过对在时间间隔中接收到的样本进行计数并潜在地对结果进行低通滤波来确定。 音频数据可以是打包的，并行的或其他形式，并且同步数据可以包括各种信号，例如以规则或不规则的间隔接收的脉冲或位。

公开(公告)号：US07576606B2

公开(公告)日：2009-08-18

申请号：US11782708

申请日：2007-07-25

申请人： Jack B. Andersen ,  Peter Craven ,  Michael A. Kost ,  Daniel L. W. Chieng ,  Larry E. Hand ,  Wilson E. Taylor

发明人： Jack B. Andersen ,  Peter Craven ,  Michael A. Kost ,  Daniel L. W. Chieng ,  Larry E. Hand ,  Wilson E. Taylor

IPC分类号： H03F3/38

CPC分类号： H03F3/217

摘要： Systems and methods for performance improvements in digital switching amplifiers using a low delay corrector. In one embodiment, a digital pulse width modulation (PWM) amplifier includes a signal processing plant configured to receive and process an input audio signal. The amplifier also includes a low delay corrector configured to receive signals output by the plant. The output of the low delay corrector is added to the input audio signal as feedback. The plant may consist of a modulator and power switch, a noise shaper, or any other type of plant. An analog-to-digital converter (ADC) may be provided to convert the output audio signal to a digital signal. Filtering may be implemented before or after the ADC, and a decimator may be placed after the ADC if it is an oversampling ADC.

摘要翻译： 使用低延迟校正器的数字开关放大器性能改进的系统和方法。 在一个实施例中，数字脉宽调制（PWM）放大器包括被配置为接收和处理输入音频信号的信号处理设备。 放大器还包括低延迟校正器，其被配置为接收由工厂输出的信号。 低延迟校正器的输出作为反馈被添加到输入音频信号。 该设备可以由调制器和电源开关，噪声整形器或任何其它类型的设备组成。 可以提供模数转换器（ADC）以将输出音频信号转换为数字信号。 可以在ADC之前或之后实现滤波，如果ADC是过采样ADC，则可以在ADC之后放置抽取器。

公开(公告)号：US07436256B2

公开(公告)日：2008-10-14

申请号：US11687455

申请日：2007-03-16

申请人： Michael A. Kost

发明人： Michael A. Kost

IPC分类号： H03F3/38

CPC分类号： H03F3/217

摘要： Systems and methods for preventing violations of minimum pulse width requirements that may cause damage to PWM amplifiers. One embodiment comprises a digital PWM amplifier that includes shutdown circuitry which is configured to identify blockout intervals during which deassertion of the PWM signals would cause the generation of below-minimum-width pulses in the signals. Each blockout interval may, for example, begin 1 minimum pulse width before and end 1 minimum pulse width after a rising/falling edge the PWM signals. If a shutdown signal is asserted (or deasserted) during one of the blockout intervals, the PWM signals are deasserted (or reasserted) at the end of the blockout interval.

摘要翻译： 防止可能造成PWM放大器损坏的最小脉冲宽度要求的系统和方法。 一个实施例包括数字PWM放大器，该数字PWM放大器包括关断电路，其被配置为识别阻塞间隔，在此间隔期间PWM信号的取消导致信号中产生低于最小宽度的脉冲。 每个阻塞间隔可以例如在PWM信号的上升沿/下降沿之后开始1个最小脉冲宽度和结束1个最小脉冲宽度。 如果在一个阻塞间隔期间关闭信号被断言（或无效），则在阻塞间隔结束时，PWM信号被置为无效（或重新置为空闲）。

公开(公告)号：US08082438B2

公开(公告)日：2011-12-20

申请号：US12202359

申请日：2008-09-01

申请人： Daniel L. Chieng ,  Douglas D. Gephardt ,  Jeffrey M. Klaas ,  Adam Zaharias

发明人： Daniel L. Chieng ,  Douglas D. Gephardt ,  Jeffrey M. Klaas ,  Adam Zaharias

IPC分类号： G06F9/00 ,  G06F1/04 ,  G06F3/00 ,  G06F13/00 ,  G06F15/00 ,  G10L19/00 ,  G10L21/04 ,  H05K7/10

CPC分类号： G06F9/4401 ,  G06F9/4408

摘要： Systems and methods for booting a programmable processor such as a DSP that is incorporated into an HDA codec. The codec and a system memory containing boot program instructions are connected to an HDA bus. In a first mode, the DSP receives boot program instructions via the HDA bus and boots using these instructions. In a second mode, the DSP boots from instructions that are contained in a memory that is connected to the DSP. In one embodiment, the memory connected to the DSP is a component of a plug-in card, and the DSP is configured to determine whether the plug-in card is present, then boot from the memory on the plug-in card if it is present or boot from the system memory via the HDA bus if the plug-in card is not present.

摘要翻译： 用于引导可编程处理器（例如并入HDA编解码器的DSP）的系统和方法。 编解码器和包含引导程序指令的系统存储器连接到HDA总线。 在第一种模式下，DSP通过HDA总线接收引导程序指令，并使用这些指令进行引导。 在第二种模式下，DSP从包含在连接到DSP的存储器中的指令引导。 在一个实施例中，连接到DSP的存储器是插件卡的组件，并且DSP被配置为确定插件卡是否存在，然后从插件卡上的存储器引导，如果它是 如果插件卡不存在，则通过HDA总线从系统存储器中显示或引导。

公开(公告)号：US07729790B1

公开(公告)日：2010-06-01

申请号：US10805590

申请日：2004-03-19

申请人： Larry E. Hand ,  Jack B. Andersen ,  Daniel L. W. Chieng ,  Michael A. Kost ,  Wilson E. Taylor

发明人： Larry E. Hand ,  Jack B. Andersen ,  Daniel L. W. Chieng ,  Michael A. Kost ,  Wilson E. Taylor

IPC分类号： G06F17/00 ,  G06F1/04 ,  H03M7/00

CPC分类号： H03M5/08 ,  H03F3/217

摘要： Systems and methods for ensuring proper phase alignment of audio signals which are processed by separate hardware channels in an audio amplification system. In one embodiment, the phase alignment is controlled by determining the number of audio data samples which are stored in the input buffers of multiple audio amplification units and controlling reads from the input buffers to minimize the difference between an actual read-write pointer differential and a target differential. In a master unit, the target differential is a predetermined target value corresponding to a desired delay in the buffer. The actual pointer differential of the master unit is passed to one or more slave units. The actual pointer differential of the master unit is used as the target differential of the slave units. The pointer differentials of the slave units are thereby driven to track the pointer differential of the master unit, keeping the units synchronized.

摘要翻译： 用于确保音频信号的适当相位对准的系统和方法，其由音频放大系统中的分开的硬件通道处理。 在一个实施例中，通过确定存储在多个音频放大单元的输入缓冲器中的音频数据样本的数量来控制相位对准，并且控制来自输入缓冲器的读取以最小化实际读写指针差和 目标差异。 在主单元中，目标差分是与缓冲器中期望的延迟对应的预定目标值。 主单元的实际指针差分传递给一个或多个从单元。 主单元的实际指针差异用作从单元的目标差。 因此，从属单元的指针差异被驱动以跟踪主单元的指针差，保持单元同步。

公开(公告)号：US07649410B2

公开(公告)日：2010-01-19

申请号：US11626569

申请日：2007-01-24

申请人： Jack B. Andersen ,  Peter G. Craven

发明人： Jack B. Andersen ,  Peter G. Craven

IPC分类号： H03F3/38

CPC分类号： H03F3/217 ,  H03F1/3264 ,  H03F3/2173 ,  H03F2200/03 ,  H03F2200/114 ,  H03F2200/351 ,  H03F2201/3236 ,  H03K17/162 ,  H03K17/6871

摘要： Systems and methods in which an ultrasonic signal is introduced into an audio signal before the audio signal is amplified by a switching amplifier. The added ultrasonic signal (e.g., a tone at half the amplifier's switching frequency) shifts the signals input to a set of power switches so that they do not switch nearly simultaneously. The ultrasonic signal causes the output current to be well defined to eliminate dead time distortion at low signal levels. Adding the tone ultrasonic signal causes the distortion to shift to an amplitude greater than zero. Signals that exceed this amplitude will experience the distortion, but the distortion will be less noticeable than in lower-amplitude signals. Signals that do not exceed this amplitude will not experience the distortion at all. Adding an ultrasonic signal may also draw energy away from the switch frequency and its harmonics to interference with AM radio reception.

摘要翻译： 在音频信号被开关放大器放大之前，将超声波信号引入到音频信号中的系统和方法。 增加的超声波信号（例如，放大器开关频率的一半处的音调）将输入的信号移动到一组电源开关，使得它们几乎不同时切换。 超声波信号使得输出电流被良好地定义，以消除低信号电平下的死区失真。 增加音调超声信号会导致失真转移到大于零的幅度。 超过该幅度的信号将经历失真，但是失真比在较低幅度信号中更不明显。 不超过此幅度的信号根本不会出现失真。 添加超声波信号也可能会从开关频率及其谐波中吸收能量，从而干扰AM无线电接收。

公开(公告)号：US07474722B1

公开(公告)日：2009-01-06

申请号：US10805591

申请日：2004-03-19

申请人： Daniel L. W. Chieng ,  Jack B. Andersen ,  Larry E. Hand

发明人： Daniel L. W. Chieng ,  Jack B. Andersen ,  Larry E. Hand

IPC分类号： H04L7/00

CPC分类号： H03F3/217 ,  H03F2200/03 ,  H03H17/0275 ,  H03H17/0642 ,  H03H17/0685

摘要： Systems and methods for using multiple rate estimate counters in converting input data streams having variable sample rates to an output sample rate that are used in processing the data streams. In one embodiment, a system includes a clock source, first and second counters coupled to the clock source and configured to count cycles for corresponding data streams, and a data processor coupled to the first and second counters. The data processor is configured to read the number of cycles counted by each of the counters between received frame sync signals and to convert the first data stream to the predetermined output sample rate based on the corresponding number of cycles counted, and to convert the second data stream to the predetermined output sample rate based on the ratio of the numbers of cycles counted in the first and second counters.

摘要翻译： 用于将具有可变采样率的输入数据流转换为用于处理数据流的输出采样率的多个速率估计计数器的系统和方法。 在一个实施例中，系统包括时钟源，耦合​​到时钟源的第一和第二计数器，并且被配置为对相应数据流计数周期，以及耦合到第一和第二计数器的数据处理器。 数据处理器被配置为读取由接收到的帧同步信号之间的每个计数器计数的周期数，并且基于相应的计数周期将第一数据流转换成预定的输出采样率，并且将第二数据 基于在第一和第二计数器中计数的周期数的比率，将其流送到预定的输出采样率。

公开(公告)号：US07425853B2

公开(公告)日：2008-09-16

申请号：US11669643

申请日：2007-01-31

申请人： Jack B. Andersen ,  Michael A. Kost

发明人： Jack B. Andersen ,  Michael A. Kost

IPC分类号： H03K3/017

CPC分类号： H03K7/08 ,  H03F3/2173 ,  H03F2200/03 ,  H03F2200/351

摘要： Systems and methods for pulse width modulating waveforms to represent asymmetric signal levels using pulses that are symmetric within their respective switching periods. One embodiment comprises a pulse width modulation system including an asymmetric correction unit and a pair of modulators. The asymmetric correction unit receives samples of an input signal and produces two separate output signals for corresponding modulators. For each sample, the asymmetric correction unit determines whether the signal level of the sample is symmetric or asymmetric. If the signal level of the sample is symmetric, the sample is forwarded to each of the modulators. If the signal level is asymmetric, the asymmetric correction unit increases one modified sample to the next higher symmetric signal level and decreases another modified sample to the next lower symmetric signal level and forwards the modified samples to the modulators.

摘要翻译： 用于脉冲宽度调制波形的系统和方法，以使用在其各自的切换周期内对称的脉冲来表示不对称信号电平。 一个实施例包括包括非对称校正单元和一对调制器的脉宽调制系统。 不对称校正单元接收输入信号的采样，并为相应的调制器产生两个分离的输出信号。 对于每个样本，不对称校正单元确定样本的信号电平是对称还是不对称。 如果样品的信号电平是对称的，则将样品转发到每个调制器。 如果信号电平不对称，则不对称校正单元将一个修改的采样增加到下一个较高的对称信号电平，并将另一个修改的采样降低到下一个较低对称信号电平，并将修改的采样转发到调制器。

公开(公告)号：US07286009B2

公开(公告)日：2007-10-23

申请号：US11324132

申请日：2005-12-30

申请人： Jack B. Andersen ,  Peter Craven ,  Michael A. Kost ,  Daniel L. W. Chieng ,  Larry E. Hand ,  Wilson E. Taylor

发明人： Jack B. Andersen ,  Peter Craven ,  Michael A. Kost ,  Daniel L. W. Chieng ,  Larry E. Hand ,  Wilson E. Taylor

IPC分类号： H03F3/68

CPC分类号： H03F3/217 ,  H03F1/32 ,  H03F2200/331

摘要： Systems and methods for performance improvements in digital switching amplifiers using simulation-based feedback. In one embodiment, a digital pulse width modulation (PWM) amplifier includes a signal processing plant configured to receive and process an input audio signal. The amplifier also includes a simulator configured to model processing of audio signals by the plant. The outputs of the plant and the simulator are provided to a subtractor, the output of which is then added to the input audio signal as feedback. The plant may consist of a modulator and power switch, a noise shaper, or any other type of plant. An analog-to-digital converter (ADC) may be provided to convert the output audio signal to a digital signal for input to the subtractor. Filtering may be implemented before or after the ADC, and a decimator may be placed after the ADC if it is an oversampling ADC.