公开(公告)号：US07027344B1

公开(公告)日：2006-04-11

申请号：US10804461

申请日：2004-03-18

申请人： Jong-Hoon Oh

发明人： Jong-Hoon Oh

IPC分类号： G11C7/00

CPC分类号： G11C7/1039 ,  G11C11/406 ,  G11C11/40603 ,  G11C2211/4065

摘要： The refresh address generator of a memory includes, in part, a counter, a multitude of shift registers and multiplexers, and a comparator. With each clock cycle, the counter increments and stores the refresh count address, and the addresses stored in the counter and the shift registers prior to the increment operation is shifted out and stored in a pipelined fashion. If the array address stored in the last stage of the register pipeline is equal to the address of the array read out during the cycle immediately preceding the refresh cycle or is equal to the address of the neighboring array of the read out array, the comparator causes multiplexer to select the address stored in the counter as the refresh address. This address differs from the address of the array read out during the immediately preceding cycle by at least two counts.

摘要翻译： 存储器的刷新地址生成器部分地包括计数器，多个移位寄存器和多路复用器以及比较器。 在每个时钟周期中，计数器递增并存储刷新计数地址，并且在增量操作之前存储在计数器和移位寄存器中的地址被移出并以流水线方式存储。 如果存储在寄存器流水线的最后一级的阵列地址等于在刷新周期之前的周期中读出的阵列的地址或等于读出阵列的相邻阵列的地址，则比较器导致 多路复用器选择存储在计数器中的地址作为刷新地址。 该地址与前一周期中读出的阵列的地址不同，至少有两个计数。

公开(公告)号：US6033945A

公开(公告)日：2000-03-07

申请号：US89928

申请日：1998-06-03

申请人： Adrian E. Ong

发明人： Adrian E. Ong

IPC分类号： G11C7/12 ,  H01L27/108 ,  H01L21/8238

CPC分类号： G11C7/12 ,  H01L27/10897 ,  Y10S438/936

摘要： According to one embodiment, a memory device comprises a bit line operable to access a memory cell. The bit line has a first end and a second end. A first equilibration circuit is coupled to the first end of the bit line, and a second equilibration circuit is coupled to the second end of the bit line. The first and second equilibration circuits cooperate to pre-charge the bit line. According to another embodiment, an embedded-process memory device comprises a p-well and a deep n-well formed into a substrate. A retrograde well is formed into the deep n-well. An equilibration circuit for pre-charging a bit line is formed into the retrograde well.

摘要翻译： 根据一个实施例，存储器设备包括可操作以访问存储器单元的位线。 位线具有第一端和第二端。 第一平衡电路耦合到位线的第一端，并且第二平衡电路耦合到位线的第二端。 第一和第二平衡电路协作以对位线预充电。 根据另一实施例，嵌入式处理存储器件包括形成衬底的p阱和深n阱。 逆深井形成深井。 在逆行井中形成用于对位线进行预充电的平衡电路。

公开(公告)号：US6031784A

公开(公告)日：2000-02-29

申请号：US148817

申请日：1998-09-04

申请人： Adrian E. Ong

发明人： Adrian E. Ong

IPC分类号： G11C7/18 ,  G11C8/14 ,  G11C7/00

CPC分类号： G11C7/18 ,  G11C8/14

摘要： In one aspect of the invention, a circuit for the hierarchical decoding of a memory device includes a local word line for accessing a memory cell. A local word line driver, which drives the local word line, has at most two transistors, each of these transistors coupled to the local word line. In another aspect of the invention, a circuit for the hierarchical decoding of a memory device includes a local word line driver for driving a local word line. A local phase line driver is connected to the local word line driver by a single metal line. The local phase line driver cooperates with the local word line driver for accessing a memory cell.

摘要翻译： 在本发明的一个方面，用于存储器件的分层解码的电路包括用于访问存储器单元的本地字线。 驱动本地字线的本地字线驱动器具有至多两个晶体管，这些晶体管中的每一个耦合到本地字线。 在本发明的另一方面，用于存储器件的分层解码的电路包括用于驱动本地字线的本地字线驱动器。 局部相线驱动器通过单个金属线连接到本地字线驱动器。 本地相线驱动器与本地字线驱动器协作以访问存储单元。

公开(公告)号：US6166976A

公开(公告)日：2000-12-26

申请号：US418959

申请日：1999-10-15

申请人： Adrian E. Ong

发明人： Adrian E. Ong

IPC分类号： G11C7/12 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C7/12 ,  H01L27/10897 ,  Y10S438/936

摘要： According to one embodiment, a memory device comprises a bit line operable to access a memory cell. The bit line has a first end and a second end. A first equilibration circuit is coupled to the first end of the bit line, and a second equilibration circuit is coupled to the second end of the bit line. The first and second equilibration circuits cooperate to pre-charge the bit line. According to another embodiment, an embedded-process memory device comprises a p-well and a deep n-well formed into a substrate. A retrograde well is formed into the deep n-well. An equilibration circuit for pre-charging a bit line is formed into the retrograde well.

公开(公告)号：US6154386A

公开(公告)日：2000-11-28

申请号：US98127

申请日：1998-06-16

申请人： Adrian E. Ong

发明人： Adrian E. Ong

IPC分类号： G11C5/06 ,  G11C7/18 ,  G11C11/4097

CPC分类号： G11C7/18 ,  G11C11/4097 ,  G11C5/06

摘要： A memory device includes a plurality of bit lines, with each bit line serving at least one respective memory cell. A plurality of input/output lines are connected and parallel to the bit lines. The input/output lines allow data to be placed upon or extracted from the bit lines. Because the I/O lines are positioned parallel, rather than perpendicular, to the bit lines, the surface area required to implement the memory device does not increase in proportion to the number of bit lines provided. Accordingly, a relatively wide data path can be implemented on the memory device without significantly increasing the amount of surface area.

摘要翻译： 存储器件包括多个位线，每个位线用于至少一个相应的存储器单元。 多个输入/输出线被连接并且与位线并联。 输入/输出线允许将数据放置在位线上或从位线中提取。 因为I / O线与位线平行而不是垂直定位，所以实现存储器件所需的表面积不会与所提供的位线数量成比例地增加。 因此，可以在存储器设备上实现相对较宽的数据路径，而不会显着增加表面积的量。

公开(公告)号：US5970020A

公开(公告)日：1999-10-19

申请号：US154664

申请日：1998-09-16

申请人： Adrian E. Ong

发明人： Adrian E. Ong

IPC分类号： G11C8/06 ,  G11C8/00

CPC分类号： G11C8/06

摘要： A circuit is provided for controlling the set up of a memory address. The circuit includes a first latch circuit for latching a first memory address in response to a first simultaneous occurrence of a predetermined value for an output enable signal and a predetermined value for a row address strobe signal. A second latch circuit is coupled to the first latch circuit. The second latch circuit receives the first memory address from the first latch circuit and latches the first row address thereafter for decoding. The first latch circuit can latch a second memory address in response to a second simultaneous occurrence of the predetermined value for the output enable signal and the predetermined value for the row address strobe signal, the second simultaneous occurrence occurring while the first row address is being decoded.

摘要翻译： 提供用于控制存储器地址的建立的电路。 电路包括用于响应于输出使能信号的预定值和行地址选通信号的预定值的第一同时出现而锁存第一存储器地址的第一锁存电路。 第二锁存电路耦合到第一锁存电路。 第二锁存电路从第一锁存电路接收第一存储器地址，然后锁存第一行地址进行解码。 第一锁存电路可以响应于输出使能信号的预定值和行地址选通信号的预定值的第二同时出现而锁存第二存储器地址，在第一行地址被解码时发生第二同时发生 。