公开(公告)号：US20150137063A1

公开(公告)日：2015-05-21

申请号：US14591170

申请日：2015-01-07

申请人： Micron Technology, Inc.

发明人： D.V. Nirmal Ramaswamy ,  Gurtej S. Sandhu

IPC分类号： H01L45/00

CPC分类号： H01L45/1246 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1616 ,  H01L45/1633 ,  Y10S438/936

摘要： Methods, devices, and systems associated with oxide based memory can include a method of forming a resistive switching region of a memory cell. Forming a resistive switching region of a memory cell can include forming a metal oxide material on an electrode and forming a metal material on the metal oxide material, wherein the metal material formation causes a reaction that results in a graded metal oxide portion of the memory cell.

摘要翻译： 与基于氧化物的存储器相关联的方法，装置和系统可以包括形成存储器单元的电阻式开关区域的方法。 形成存储单元的电阻开关区域可以包括在电极上形成金属氧化物材料并在金属氧化物材料上形成金属材料，其中金属材料形成引起导致存储单元的分级金属氧化物部分的反应 。

公开(公告)号：US08951829B2

公开(公告)日：2015-02-10

申请号：US13078679

申请日：2011-04-01

申请人： D.V. Nirmal Ramaswamy ,  Gurtej S. Sandhu

发明人： D.V. Nirmal Ramaswamy ,  Gurtej S. Sandhu

IPC分类号： H01L27/112 ,  H01L45/00

CPC分类号： H01L45/1246 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1616 ,  H01L45/1633 ,  Y10S438/936

摘要： Methods, devices, and systems associated with oxide based memory can include a method of forming a resistive switching region of a memory cell. Forming a resistive switching region of a memory cell can include forming a metal oxide material on an electrode and forming a metal material on the metal oxide material, wherein the metal material formation causes a reaction that results in a graded metal oxide portion of the memory cell.

摘要翻译： 与基于氧化物的存储器相关联的方法，装置和系统可以包括形成存储器单元的电阻式开关区域的方法。 形成存储单元的电阻开关区域可以包括在电极上形成金属氧化物材料并在金属氧化物材料上形成金属材料，其中金属材料形成引起导致存储单元的分级金属氧化物部分的反应 。

公开(公告)号：US07842973B2

公开(公告)日：2010-11-30

申请号：US11485287

申请日：2006-07-13

申请人： Makoto Miura ,  Katsuyoshi Washio ,  Hiromi Shimamoto

发明人： Makoto Miura ,  Katsuyoshi Washio ,  Hiromi Shimamoto

IPC分类号： H01L29/737 ,  H01L21/331

CPC分类号： H01L29/7378 ,  Y10S438/936

摘要： A semiconductor device capable of avoiding generation of a barrier in a conduction band while maintaining high withstanding voltage and enabling high speed transistor operation at high current in a double hetero bipolar transistor, as well as a manufacturing method thereof, wherein a portion of the base and the collector is formed of a material with a forbidden band width narrower than that of a semiconductor substrate, a region where the forbidden band increases stepwise and continuously from the emitter side to the collector side is disposed in the inside of the base and the forbidden band width at the base-collector interface is designed so as to be larger than the minimum forbidden band width in the base, whereby the forbidden band width at the base layer edge on the collector side can be made closer to the forbidden band width of the semiconductor substrate than usual while sufficiently maintaining the hetero effect near the emitter-base thereby capable of decreasing the height of the energy barrier generated upon increase of the collector current and enabling satisfactory transistor operation at high current.

摘要翻译： 一种半导体器件及其制造方法，其能够在保持高耐受电压的同时避免在导带中产生阻挡层并能够在高电流下进行高速晶体管的操作，以及其制造方法，其中， 集电体由禁带宽度窄于半导体衬底的材料形成，禁带从发射极侧向集电极侧逐步且连续地增加的区域设置在基体的内部，禁带 在基极集电体界面的宽度被设计为大于基极中的最小禁带宽度，由此集电极侧的基底边缘处的禁带宽度可以更接近半导体的禁带宽度 衬底，同时充分保持发射极基极附近的杂质效应，从而能够降低高度 在集电极电流增加时产生能量势垒，并且能够在高电流下令人满意的晶体管工作。

公开(公告)号：US07598513B2

公开(公告)日：2009-10-06

申请号：US10559979

申请日：2004-06-14

申请人： John Kouvetakis ,  Matthew Bauer ,  John Tolle

发明人： John Kouvetakis ,  Matthew Bauer ,  John Tolle

IPC分类号： H01L29/06 ,  H01L21/336

CPC分类号： H01L31/028 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/0259 ,  H01L21/0262 ,  H01L29/161 ,  H01L29/165 ,  Y02E10/547 ,  Y10S148/169 ,  Y10S438/936

摘要： A novel method for synthesizing device-quality alloys and ordered phases in a Si—Ge—Sn system uses a UHV-CVD process and reactions of SnD4 with SiH3GeH3. Using the method, single-phase SixSnyGe1-x-y semiconductors (x≦0.25, y≦0.11) are grown on Si via Ge1-xSnx buffer layers The Ge1-xSnx buffer layers facilitate heteroepitaxial growth of the SixSnyGe1-x-y films and act as compliant templates that can conform structurally and absorb the differential strain imposed by the more rigid Si and Si—Ge—Sn materials. The SiH3GeH3 species was prepared using a new and high yield method that provided high purity semiconductor grade material.

摘要翻译： 在Si-Ge-Sn系统中合成器件质量合金和有序相的新方法使用特高压CVD法和SnD4与SiH3GeH3的反应。 使用该方法，通过Ge1-xSnx缓冲层在Si上生长单相SixSnyGe1-xy半导体（x <= 0.25，y <= 0.11）。Ge1-xSnx缓冲层促进SixSnyGe1-xy膜的异质外延生长，并作为 可以在结构上符合并吸收由更刚性的Si和Si-Ge-Sn材料施加的微分应变。 使用提供高纯度半导体级材料的新的高产率方法制备SiH 3 GeH 3物质。

公开(公告)号：US07487050B2

公开(公告)日：2009-02-03

申请号：US11432663

申请日：2006-05-10

申请人： Ares J. Rosakis ,  Yonggang Huang

发明人： Ares J. Rosakis ,  Yonggang Huang

IPC分类号： G01L1/00

CPC分类号： G01L5/0047 ,  Y10S438/936

摘要： Techniques and devices are described to use spatially-varying curvature information of a layered structure to determine stresses at each location with non-local contributions from other locations of the structure. For example, a local contribution to stresses at a selected location on a layered structure formed on a substrate is determined from curvature changes at the selected location and a non-local contribution to the stresses at the selected location is also determined from curvature changes at all locations across the layered structure. Next, the local contribution and the non-local contribution are combined to determine the total stresses at the selected location. Techniques and devices for determining a misfit strain between a film and a substrate on which the film is deposited are also described.

摘要翻译： 技术和装置被描述为使用分层结构的空间变化的曲率信息来确定每个位置处的应力，其中非局部贡献来自该结构的其他位置。 例如，根据在所选择的位置处的曲率变化来确定在基板上形成的层状结构上的选定位置处的应力的局部贡献，并且还根据曲率变化确定对所选位置处的应力的非局部贡献 分层结构的位置。 接下来，组合本地贡献和非本地贡献以确定所选位置处的总应力。 还描述了用于确定薄膜和沉积薄膜的基板之间的失配应变的技术和装置。

公开(公告)号：US07459716B2

公开(公告)日：2008-12-02

申请号：US11761333

申请日：2007-06-11

申请人： Haruki Toda ,  Koichi Kubo

发明人： Haruki Toda ,  Koichi Kubo

IPC分类号： H01L29/02 ,  G11C11/00

CPC分类号： G11C13/0007 ,  G11C5/02 ,  G11C13/0004 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/34 ,  G11C2213/55 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/147 ,  Y10S438/936

摘要： A resistance change memory device including: a semiconductor substrate; cell arrays stacked above the substrate, bit lines word lines; a read/write circuit formed on the semiconductor substrate; first and second vertical wirings disposed to connect the bit lines to the read/write circuit; and third vertical wirings disposed to connect the word lines to the read/write circuit, wherein the memory cell includes a variable resistance element for storing as information a resistance value, which has a recording layer formed of a first composite compound expressed by AxMyOz (where “A” and “M” are cation elements different from each other; “O” oxygen; and 0.5≦x≦1.5, 0.5≦y≦2.5 and 1.5≦z≦4.5) and a second composite compound containing at least one transition element and a cavity site for housing a cation ion.

摘要翻译： 一种电阻变化存储器件，包括：半导体衬底; 单元阵列堆叠在基板上方，位线字线; 形成在半导体衬底上的读/写电路; 布置成将位线连接到读/写电路的第一和第二垂直布线; 以及第三垂直布线，用于将字线连接到读/写电路，其中存储单元包括可变电阻元件，用于存储作为信息的电阻值，该电阻值具有由AxMyOz表示的第一复合化合物形成的记录层（其中 “A”和“M”是彼此不同的阳离子元素;“O”氧; 0.5 <= x <= 1.5,0.5 <= y <= 2.5和1.5 <= z <= 4.5）和第二复合化合物 含有至少一个过渡元素和用于容纳阳离子离子的空腔部位。

公开(公告)号：US20070285965A1

公开(公告)日：2007-12-13

申请号：US11761333

申请日：2007-06-11

申请人： Haruki Toda ,  Koichi Kubo

发明人： Haruki Toda ,  Koichi Kubo

IPC分类号： G11C11/36

CPC分类号： G11C13/0007 ,  G11C5/02 ,  G11C13/0004 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/34 ,  G11C2213/55 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/147 ,  Y10S438/936

摘要： A resistance change memory device including: a semiconductor substrate; cell arrays stacked above the substrate, bit lines word lines; a read/write circuit formed on the semiconductor substrate; first and second vertical wirings disposed to connect the bit lines to the read/write circuit; and third vertical wirings disposed to connect the word lines to the read/write circuit, wherein the memory cell includes a variable resistance element for storing as information a resistance value, which has a recording layer formed of a first composite compound expressed by AxMyOz (where “A” and “M” are cation elements different from each other; “O” oxygen; and 0.5≦x≦1.5, 0.5≦y≦2.5 and 1.5≦z≦4.5) and a second composite compound containing at least one transition element and a cavity site for housing a cation ion.

摘要翻译： 一种电阻变化存储器件，包括：半导体衬底; 单元阵列堆叠在基板上方，位线字线; 形成在半导体衬底上的读/写电路; 布置成将位线连接到读/写电路的第一和第二垂直布线; 以及第三垂直布线，用于将字线连接到读/写电路，其中存储单元包括可变电阻元件，用于存储作为信息的电阻值，该电阻值具有由A

公开(公告)号：US20040219703A1

公开(公告)日：2004-11-04

申请号：US10785747

申请日：2004-02-23

发明人： David P. Bour ,  Tetsuya Takeuchi ,  Ashish Tandon ,  Ying-Lan Chang ,  Michael R. T. Tan ,  Scott W. Corzine

IPC分类号： H01L021/00

CPC分类号： C30B25/02 ,  C30B29/403 ,  H01L21/02395 ,  H01L21/02463 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/02546 ,  H01L21/0262 ,  H01L33/007 ,  H01L33/105 ,  H01S5/32366 ,  Y10S438/936 ,  Y10S438/938 ,  Y10S438/956

摘要： The active region of a long-wavelength light emitting device is made by providing an organometallic vapor phase epitaxy (OMVPE) reactor, placing a substrate wafer capable of supporting growth of indium gallium arsenide nitride in the reactor, supplying a Group III-V precursor mixture comprising an arsenic precursor, a nitrogen precursor, a gallium precursor, an indium precursor and a carrier gas to the reactor and pressurizing the reactor to a sub-atmospheric elevated growth pressure no higher than that at which a layer of indium gallium arsenide layer having a nitrogen fraction commensurate with light emission at a wavelength longer than 1.2 nullm is deposited over the substrate wafer.

摘要翻译： 通过提供有机金属气相外延（OMVPE）反应器，将能够支持砷化镓镓氮化物的生长的衬底晶片放置在反应器中，提供III-V族前体混合物，制造长波长发光器件的有源区 包括砷前体，氮前体，镓前体，铟前体和载气，并将反应器加压至不高于砷化镓砷化物层的亚大气压升高的生长压力 在基片晶片上沉积与长于1.2μm波长的发光相当的氮气分数。

公开(公告)号：US06794211B2

公开(公告)日：2004-09-21

申请号：US10101800

申请日：2002-03-20

申请人： Myeong Seok Oh ,  Sung Wook Lim ,  Jeong Hwan Ahn

发明人： Myeong Seok Oh ,  Sung Wook Lim ,  Jeong Hwan Ahn

IPC分类号： H01L2100

CPC分类号： H01L33/30 ,  H01L33/105 ,  H01L33/14 ,  Y10S438/936

摘要： The light emitting diode includes an intermediate layer made of non-single crystalline material between single crystalline layers. By the intermediate layer, the boundary characteristic between the single crystalline layers may be improved and the defect caused by the lattice mismatch can be decreased, so that the brightness and forward voltage characteristics can be improved.

摘要翻译： 发光二极管包括在单晶层之间由非单晶材料制成的中间层。 通过中间层，可以提高单晶层之间的边界特性，并且可以减小由晶格失配引起的缺陷，从而可以提高亮度和正向电压特性。

公开(公告)号：US06703300B2

公开(公告)日：2004-03-09

申请号：US10112088

申请日：2002-03-29

申请人： Thomas N. Jackson

发明人： Thomas N. Jackson

IPC分类号： H01L21265

CPC分类号： C23C14/225 ,  B82Y10/00 ,  B82Y30/00 ,  H01L21/32051 ,  Y10S438/936

摘要： There is a method for forming a multilayer electronic device. The method has the following steps: a) depositing a thin molecular layer on an electrically conductive substrate and b) depositing metal atoms or ions on the thin molecular layer at an angle of about 60 degrees or less with respect to the plane of the exposed surface of the thin molecular layer.

摘要翻译： 存在形成多层电子器件的方法。 该方法具有以下步骤：a）在导电基底上沉积薄分子层，和b）相对于暴露表面的平面以大约60度或更小的角度在薄分子层上沉积金属原子或离子 的薄分子层。