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    Method and apparatus to reduce power consumption by transferring functionality from memory components to a memory interface
    1.
    发明授权
    Method and apparatus to reduce power consumption by transferring functionality from memory components to a memory interface 有权
    通过将功能从存储器组件传送到存储器接口来降低功耗的方法和装置

    公开(公告)号：US08797811B2

    公开(公告)日：2014-08-05

    申请号：US12273348

    申请日：2008-11-18

    申请人： Jong-Hoon Oh

    发明人： Jong-Hoon Oh

    IPC分类号： G11C7/00 ,  G11C7/10 ,  H03L7/081 ,  G11C7/22 ,  G11C8/18

    CPC分类号： G11C8/18 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/225 ,  G11C2207/2227 ,  H03L7/0812

    摘要： A common Delay Locked Loop (DLL) circuit and/or voltage generator circuit is provided in, or associated with. a memory interface interposed between a memory controller and a plurality of memory components. Corresponding circuits in the memory components are disabled and/or bypassed, or the memory components are manufactured without the circuits. Both the DLL circuit and voltage generator draw current, which is multiplied by the number of memory components in a memory system. By operating a single DLL circuit and/or voltage generator in or associated with the memory interface, that generates a read clock signal and/or various voltage levels, respectively, for all memory components in the memory system, power consumption may be significantly reduced.

    摘要翻译： 一个常见的延迟锁定环路（DLL）电路和/或电压发生器电路被提供在或与之相关联。 插入在存储器控制器和多个存储器组件之间的存储器接口。 存储器组件中的相应电路被禁用和/或旁路，或者存储器组件在没有电路的情况下被制造。 DLL电路和电压发生器都会抽出电流，该电流乘以存储器系统中的存储器组件的数量。 通过在存储器接口中操作单独的DLL电路和/或电压发生器，分别为存储器系统中的所有存储器组件生成读取时钟信号和/或各种电压电平，可以显着降低功耗。

    Computing circuits and method for running an MPEG-2 AAC or MPEG-4 AAC audio decoding algorithm on programmable processors
    2.
    发明授权
    Computing circuits and method for running an MPEG-2 AAC or MPEG-4 AAC audio decoding algorithm on programmable processors 有权
    用于在可编程处理器上运行MPEG-2 AAC或MPEG-4AAC音频解码算法的计算电路和方法

    公开(公告)号：US08200730B2

    公开(公告)日：2012-06-12

    申请号：US12880720

    申请日：2010-09-13

    申请人： Jong Hoon Oh ,  Myung Hoon Sunwoo ,  Jong Ha Moon

    发明人： Jong Hoon Oh ,  Myung Hoon Sunwoo ,  Jong Ha Moon

    IPC分类号： G06F17/14

    CPC分类号： G10L19/16

    摘要： The present invention relates to computing circuits and method for running an MPEG-2 AAC or MPEG-4 AAC algorithm efficiently, which is used as an audio compression algorithm in multi-channel high-quality audio systems, on programmable processors. In accordance with the present invention, the IMDCT process which takes large part of the amount of the operations in implementation of an MPEG-2/4 AAC algorithm can be performed in efficient. In addition, while the architecture of the existing digital signal processor is still used, the performance can be improved by means of the addition of the architecture of the address generator, Huffman decoder, and bit processing architecture. After all, to design and change the programmable processor is facilitated.

    摘要翻译： 本发明涉及用于在可编程处理器上用作多声道高质量音频系统中的音频压缩算法的有效运行MPEG-2AAC或MPEG-4AAC算法的计算电路和方法。 根据本发明，可以有效地执行在实施MPEG-2 / 4AAC算法中占用大量部分操作的IMDCT处理。 另外，虽然现有的数字信号处理器的架构仍然被使用，但是通过添加地址生成器，霍夫曼解码器和位处理架构的架构，可以提高性能。 毕竟，设计和改变可编程处理器是方便的。

    System memory device having a dual port
    4.
    发明授权
    System memory device having a dual port 有权
    具有双端口的系统存储设备

    公开(公告)号：US07725609B2

    公开(公告)日：2010-05-25

    申请号：US11198366

    申请日：2005-08-05

    申请人： Jong-Hoon Oh

    发明人： Jong-Hoon Oh

    IPC分类号： G06F3/00 ,  G06F12/00

    CPC分类号： G06F13/1663

    摘要： A computing system having a plurality of processors including a first processor configured with an address port and a second processor configured with an address port, and a memory device having a first port configured as an address port and to alternatively interface with the address port of the first processor and the address port of the second processor.

    摘要翻译： 一种具有多个处理器的计算系统，包括配置有地址端口的第一处理器和配置有地址端口的第二处理器，以及具有配置为地址端口的第一端口和与所述地址端口的地址端口交替接口的存储器件 第一处理器和第二处理器的地址端口。

    Method and Apparatus to Reduce Power Consumption by Transferring Functionality from Memory Components to a Memory Interface
    5.
    发明申请
    Method and Apparatus to Reduce Power Consumption by Transferring Functionality from Memory Components to a Memory Interface 有权
    通过将功能从存储器组件传输到存储器接口来降低功耗的方法和装置

    公开(公告)号：US20100124130A1

    公开(公告)日：2010-05-20

    申请号：US12273348

    申请日：2008-11-18

    申请人： Jong-Hoon Oh

    发明人： Jong-Hoon Oh

    IPC分类号： G11C7/00 ,  G11C8/18

    CPC分类号： G11C8/18 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/225 ,  G11C2207/2227 ,  H03L7/0812

    摘要： A common Delay Locked Loop (DLL) circuit and/or voltage generator circuit is provided in, or associated with. a memory interface interposed between a memory controller and a plurality of memory components. Corresponding circuits in the memory components are disabled and/or bypassed, or the memory components are manufactured without the circuits. Both the DLL circuit and voltage generator draw current, which is multiplied by the number of memory components in a memory system. By operating a single DLL circuit and/or voltage generator in or associated with the memory interface, that generates a read clock signal and/or various voltage levels, respectively, for all memory components in the memory system, power consumption may be significantly reduced.

    摘要翻译： 一个常见的延迟锁定环路（DLL）电路和/或电压发生器电路被提供在或与之相关联。 插入在存储器控制器和多个存储器组件之间的存储器接口。 存储器组件中的相应电路被禁用和/或旁路，或者存储器组件在没有电路的情况下被制造。 DLL电路和电压发生器都会抽出电流，该电流乘以存储器系统中的存储器组件的数量。 通过在存储器接口中操作单独的DLL电路和/或电压发生器，分别为存储器系统中的所有存储器组件生成读取时钟信号和/或各种电压电平，可以显着降低功耗。

    Technique to read special mode register
    8.
    发明授权
    Technique to read special mode register 失效
    技术读取特殊模式寄存器

    公开(公告)号：US07610455B2

    公开(公告)日：2009-10-27

    申请号：US11126684

    申请日：2005-05-11

    申请人： Jong-Hoon Oh

    发明人： Jong-Hoon Oh

    IPC分类号： G06F9/26 ,  G06F9/34 ,  G06F12/00 ,  G06F13/00 ,  G06F13/28

    CPC分类号： G06F13/4243

    摘要： Embodiments are provided in which a method and apparatus for accessing a special mode register of a memory device are described. A command to access the special mode register is detected. The command is executed by driving data from the special mode register onto a data bus. The command self-terminates by placing the data bus in a high impedance state. One or more unused address bits may specify one of a plurality of special mode registers to be accessed by the command. The command to access the special mode register may be incapable of changing one or more bits in a mode register.

    摘要翻译： 提供了一种用于访问存储器件的特殊模式寄存器的方法和装置的实施例。 检测到访问特殊模式寄存器的命令。 通过将数据从特殊模式寄存器驱动到数据总线上来执行命令。 通过将数据总线置于高阻抗状态，该命令自动终止。 一个或多个未使用的地址位可以指定由命令访问的多个特殊模式寄存器中的一个。 访问特殊模式寄存器的命令可能无法更改模式寄存器中的一个或多个位。

    Digital amplifier, pulse width modulator thereof and method for reducing pop noise for the same
    9.
    发明授权
    Digital amplifier, pulse width modulator thereof and method for reducing pop noise for the same 有权
    数字放大器，其脉冲宽度调制器和用于减少其噪声的方法

    公开(公告)号：US07508873B2

    公开(公告)日：2009-03-24

    申请号：US11192293

    申请日：2005-07-28

    申请人： Tae Ho Kim ,  Jong Hoon Oh

    发明人： Tae Ho Kim ,  Jong Hoon Oh

    IPC分类号： H03K7/08 ,  H03K9/08

    CPC分类号： H03F3/217 ,  H03F1/26 ,  H03F1/305 ,  H03F2200/342 ,  H03F2200/351

    摘要： A pulse width modulator for use in a digital amplifier, includes a pop noise reducer for reducing pop noise by controlling a width and a phase of a pulse of a PWM signal output from the pulse width modulator, wherein the pop noise reducer contains: a PWM pulse register for storing a width and a phase values of a pulse of the PWM signal; and a pulse generator for outputting the PWM signal according to the values stored in the PWM pulse register. The pulse width modulator reduces pop noise generated when power supply to a digital amplifier is started and interrupted.

    摘要翻译： 一种用于数字放大器的脉冲宽度调制器，包括一个用于通过控制从脉宽调制器输出的PWM信号的脉冲宽度和相位来减少弹出噪声的弹出式噪声减小器，其中弹出噪声减小器包括：PWM 脉冲寄存器，用于存储PWM信号的脉冲的宽度和相位值; 以及用于根据存储在PWM脉冲寄存器中的值输出PWM信号的脉冲发生器。 脉冲宽度调制器可以减少对数字放大器的电源开始和中断时产生的弹出噪声。