-
公开(公告)号：US09979582B1
公开(公告)日：2018-05-22
申请号：US15673228
申请日：2017-08-09
CPC分类号： H04L27/2666 , H03M1/06 , H03M1/121 , H03M3/496 , H04B2001/0491 , H04L5/0008 , H04L27/2092 , H04L2027/0081
摘要： A multi-zone analog-to-digital converter (ADC) is provided that includes a track-and-hold (T/H) stage having a bandwidth of L Hertz (Hz) to accept an analog input signal, a clock input to accept a clock signal with a clock frequency of P Hz, and N deinterleaved signal outputs with a combined bandwidth of M Hz. N×(P/2)=M, L>Q×M, and Q is an integer >1. The T/H stage is able to sample an analog input signal in the Qth Nyquist Zone, where Q is an integer. A quantizer stage has N interleaved signal inputs connected to corresponding T/H stage signal outputs, a clock input to accept the clock signal, and an output to supply a digital output signal having a bandwidth of M Hz. A packaging interface typically connects the T/H stage to the quantizer stage, and has a bandwidth less than the clock frequency.
-
公开(公告)号：US09912344B1
公开(公告)日：2018-03-06
申请号：US15706732
申请日：2017-09-17
发明人： Mikko Waltari
CPC分类号： H03M1/0624 , H03M1/50
摘要： A sort-and-delay time-to-digital converter (TDC) is provided, made up of a plurality of serially connected sort-and-delay circuits. Each sort-and-delay circuit accepts a time-differential input signal with a first edge separated from a second edge by an input duration of time. The first and second edges are selectively routed as a time-differential output signal with a delayed edge separated from a trailing edge by an output duration of time representing a compression of the input duration of time. Each sort-and-delay circuit also supplies a TDC coded bit (e.g., Gray code) indicating the order in which the first and second edges are routed as leading and trailing edges. The TDC outputs a digital output signal representing the initial input duration of time associated with the initial time-differential input signal received by the initial sort-and-delay circuit. Associated TDC, sort-and-delay, and time amplification methods are also provided.
-
公开(公告)号：US09831888B1
公开(公告)日：2017-11-28
申请号：US15614705
申请日：2017-06-06
发明人： Mikko Waltari
CPC分类号： H03M1/0624 , H03M1/50
摘要： A sort-and-delay time-to-digital converter (TDC) is provided, made up of a plurality of serially connected sort-and-delay circuits. Each sort-and-delay circuit accepts a time-differential input signal with a first edge separated from a second edge by an input duration of time. The first and second edges are selectively routed as a time-differential output signal with a delayed edge separated from a trailing edge by an output duration of time representing a compression of the input duration of time. Each sort-and-delay circuit also supplies a TDC coded bit (e.g., Gray code) indicating the order in which the first and second edges are routed as leading and trailing edges. The TDC outputs a digital output signal representing the initial input duration of time associated with the initial time-differential input signal received by the initial sort-and-delay circuit. Associated TDC, sort-and-delay, and time amplification methods are also provided.
-
-
搜索结果
3 条记录 (耗时 0.011 秒)
