-
公开(公告)号：US07188274B2
公开(公告)日：2007-03-06
申请号：US10774512
申请日：2004-02-10
IPC分类号： G06F11/00
CPC分类号： G11C29/4401 , G11C29/44 , G11C29/72
摘要： A method and circuit for repairing a memory array having one or more memory segments each having one spare column and a predetermined number of spare rows common to all segments, the method comprises, while testing the memory array for failures, generating an equal number of unique segment repair solutions for each segment with each segment repair solution including one defective column address, if any, and a number of defective row addresses, if any, corresponding to the predetermined number of spare rows; and, after completing testing, analyzing all segment repair solution combinations consisting of one segment repair solution selected from each segment; and identifying the best segment repair solution combination of combinations having a number of different defective row addresses which is less than or equal to the predetermined number of spare rows.
摘要翻译： 一种用于修复具有一个或多个存储器段的存储器阵列的方法和电路，每个存储器段具有一个备用列和预定数量的所有段公用的备用行，该方法包括在测试存储器阵列以获得故障时产生相等数量的唯一 每个段的段修复解决方案，其中每个段修复解决方案包括与预定数量的备用行相对应的一个缺陷列地址（如果有的话）和若干有缺陷的行地址（如果有的话）; 在完成测试后，分析由每个部分选择的一个部分修复解决方案组成的所有段修复解决方案组合; 以及识别具有小于或等于预定数量的备用行的具有多个不同缺陷行地址的组合的最佳段修复方案组合。
-
公开(公告)号：US07103860B2
公开(公告)日：2006-09-05
申请号：US10349452
申请日：2003-01-23
申请人： Paul Price , Jean-François Côté , Ajit Kumar Verma
发明人： Paul Price , Jean-François Côté , Ajit Kumar Verma
IPC分类号： G06F17/50
CPC分类号： G01R31/318314 , G01R31/318307 , G01R31/318357 , G06F17/5022
摘要： A program product for use in generating test benches for verifying test structures embedded in a circuit, comprises a verification specification processor for parsing a verification specification containing test specifications for selected test structures and a test bench generator for each of one or more types of embedded test structures, each test bench generator being operable to process a test structure specification of a test structure of a corresponding test structure type and generate a test bench using data contained in said test specifications of said verification specification, data contained in said test structure specification and data contained in a test connection specification.
-
公开(公告)号：US20050240847A1
公开(公告)日：2005-10-27
申请号：US11013319
申请日：2004-12-17
IPC分类号： G01R31/28 , G01R31/3185 , G01R31/319
CPC分类号： G01R31/31858 , G01R31/318552 , G01R31/31922
摘要： A test clock controller for generating a test clock signal for scan chains in integrated circuits having one or more clock domains, comprises a shift clock controller for generating a shift clock signal for use in loading test patterns into scan chains in the clock domains and for unloading a test response patterns from the scan chains and for generating a burst phase signal after loading a test pattern; and a burst clock controller associated with each of one or more clock domains and responsive to a burst phase signal for generating a burst of clock pulses derived from a respective reference clocks and including a first group of burst clock pulses having a selected reduced frequency relative to the reference clock and a second group of burst clock pulses having a frequency corresponding to that of the reference clock.
摘要翻译： 一种测试时钟控制器，用于在具有一个或多个时钟域的集成电路中产生用于扫描链的测试时钟信号，包括移位时钟控制器，用于产生用于将测试模式加载到时钟域中的扫描链中并用于卸载的移位时钟信号 来自扫描链的测试响应模式并且用于在加载测试模式之后产生突发相位信号; 以及突发时钟控制器，其与一个或多个时钟域中的每一个相关联，并且响应于脉冲串相位信号，用于产生从各个参考时钟导出的时钟脉冲串，并且包括相对于相对参考时钟具有选定的降低的频率的第一组脉冲串时钟脉冲 参考时钟和具有与参考时钟的频率对应的频率的第二组突发时钟脉冲。
-
4.发明申请Method and circuit for testing high frequency mixed signal circuits with low frequency signals 失效用于测试低频信号的高频混合信号电路的方法和电路公开(公告)号：US20030071606A1
公开(公告)日：2003-04-17
申请号：US10300620
申请日：2002-11-21
申请人： LOGICVISION, INC.
发明人： Stephen K. Sunter
IPC分类号： G01R013/14
CPC分类号： G01R31/3167
摘要： A method of testing an analog, or mixed analog and digital, circuit designed for operation at a clock frequency comprises multiplexing a plurality of low frequency stimulus signals using a high frequency clock to produce a circuit input signal, applying the input signal to the circuit to obtain a circuit output signal; sampling the circuit output signal synchronously with the high frequency clock at a frequency equal to the clock frequency divided by the number of the low frequency signals; storing the samples and measuring properties of the signal samples to determine properties of the output signal of the circuit.
摘要翻译： 一种测试设计用于在时钟频率下操作的模拟或混合模拟和数字电路的方法包括使用高频时钟多路复用多个低频激励信号以产生电路输入信号，将该输入信号施加到电路 获得电路输出信号; 以与时钟频率相等的频率除以低频信号的数量与高频时钟同步地对电路输出信号进行采样; 存储样本和测量信号样本的属性以确定电路的输出信号的特性。
-
公开(公告)号：US07257733B2
公开(公告)日：2007-08-14
申请号：US10868208
申请日：2004-06-16
IPC分类号： G06F11/00
CPC分类号： G11C29/846 , G11C29/44 , G11C29/4401 , G11C29/848
摘要： A self-repair circuit for a semiconductor memory provides input and output test selectors coupled to respective data bit group inputs and outputs, respectively and input and output repair selectors coupled between the input and output test selectors and functional inputs and functional outputs, respectively. This arrangement allows all data bit groups to be tested in one pass and all test and repair selector circuitry to be tested.
摘要翻译： 用于半导体存储器的自修复电路分别提供耦合到相应数据位组输入和输出的输入和输出测试选择器，以及耦合在输入和输出测试选择器以及功能输入和功能输出之间的输入和输出修复选择器。 这种布置允许所有数据位组在一次通过中进行测试，所有测试和修复选择器电路都要进行测试。
-
6.发明授权Circuit and method for adding parametric test capability to digital boundary scan 有权将参数化测试能力加入数字边界扫描的电路和方法公开(公告)号：US07159159B2
公开(公告)日：2007-01-02
申请号：US10414309
申请日：2003-04-16
申请人： Stephen K. Sunter
发明人： Stephen K. Sunter
IPC分类号： G01R31/28
CPC分类号： G01R31/3167 , G01R31/3012 , G01R31/318533
摘要： A boundary scan cell for use in a circuit having a boundary scan shift register (BSSR) having boundary scan cells associated with pins of the circuit, the cell having a single-bit shift register element and an associated update latch, comprises a logic circuit for controlling the logic state of an associated pin, analog switches connecting the associated pin to analog test buses, and logic circuitry for selectively configuring the cell in a parametric test mode in which the cell shift register element controls the analog switches, and in a digital test mode in which the cell shift register element controls the logic state of the associated pin.
摘要翻译： 一种边界扫描单元，用于具有边界扫描移位寄存器（BSSR）的电路，边界扫描移位寄存器（BSSR）具有与电路的引脚相关联的边界扫描单元，该单元具有单位移位寄存器元件和相关联的更新锁存器， 控制相关引脚的逻辑状态，将相关引脚连接到模拟测试总线的模拟开关和用于在参数测试模式中选择性地配置单元的逻辑电路，其中单元移位寄存器元件控制模拟开关，并且在数字测试 模式，其中单元移位寄存器元件控制相关引脚的逻辑状态。
-
公开(公告)号：US20050240848A1
公开(公告)日：2005-10-27
申请号：US11109844
申请日：2005-04-20
IPC分类号： G01R31/28 , G01R31/3185
CPC分类号： G01R31/318572
摘要： A masking circuit for selectively masking scan chain inputs and/or outputs during scan testing of an integrated circuit, comprises a mask register having at least two mask register elements for each scan chain to provide a plurality of masking modes; and an input and output mask control circuit for each scan chain, each mask control circuit being connected between a test pattern source and a signature register and between a serial input and a serial output of an associated scan chain and being responsive to mask control data stored in the register elements for configuring the associated scan chain in one of the plurality of masking modes during a scan test of the circuit.
摘要翻译： 一种屏蔽电路，用于在集成电路的扫描测试期间有选择地屏蔽扫描链输入和/或输出，包括屏蔽寄存器，其具有用于每个扫描链的至少两个屏蔽寄存器元件，以提供多个屏蔽模式; 以及用于每个扫描链的输入和输出掩模控制电路，每个掩模控制电路连接在测试图案源和签名寄存器之间，并且连接在相关联的扫描链的串行输入和串行输出之间，并响应于存储的掩码控制数据 在用于在电路的扫描测试期间用于将多个掩模模式中的一个掩模模式中的一个配置为关联的扫描链的寄存器元件中。
-
8.发明申请Clocking methodology for at-speed testing of scan circuits with synchronous clocks 有权具有同步时钟的扫描电路的高速测试时钟方法公开(公告)号：US20050240790A1
公开(公告)日：2005-10-27
申请号：US11060407
申请日：2005-02-18
IPC分类号： G01R31/3185 , G06F13/42
CPC分类号： G01R31/31858
摘要： A clocking method for at-speed scan testing for delay defects in cross-domain paths of interacting synchronous clock domains in a scan circuit, each path originating from a source memory element in one of the domains and terminating at a destination memory element in another of the domains and comprises selectively aligning either a capture edge or a launch edge of the clock of each domain with a corresponding edge of at least one other domain of the interacting synchronous clock domains to determine the cross-domain paths to be tested between a source domain and a destination domain; clocking memory elements in each domain at respective domain clock rates to launch signal transitions from source memory elements in source domains; and for each pair of interacting clock domains under test, capturing, in the destination domain, circuit responses to signal transitions launched along paths originating from the source domain and selectively disabling capturing, in the source domain, of circuit responses to signal transitions launched along paths originating from the destination domain.
摘要翻译： 一种用于对扫描电路中相互作用的同步时钟域的跨域路径中的延迟缺陷进行高速扫描测试的时钟方法，每个路径源自一个域中的源存储器元件，并终止于另一个的另一个中的目的地存储器元件 所述域并且包括选择性地将每个域的时钟的捕获边缘或启动边缘与交互的同步时钟域的至少一个其他域的相应边缘对准，以确定要在源域之间测试的跨域路径 和目的域; 以各个域时钟速率在每个域中计时存储器元件以从源域中的源存储器元件启动信号转换; 并且对于正在测试的每对相互作用的时钟域，在目的地域中捕获对源自源域的路径发射的信号转换的电路响应，并且选择性地禁止在源域中捕获沿着路径发射的信号转换的电路响应 源自目的地域。
-
公开(公告)号：US07219282B2
公开(公告)日：2007-05-15
申请号：US10701479
申请日：2003-11-06
IPC分类号： G01R31/28
CPC分类号： G01R31/318566 , G01R31/318583
摘要： A circuit and a method are provided for testing the enable function of Boundary Scan Register bits that control the driver of unconnected I/O pins of an 1149.1-compliant IC during the IC's reduced pin-count access manufacturing test, and to test the connections to these pins during the test of a circuit board containing the IC, without causing excessive current if a pin is inadvertently short circuited.
摘要翻译： 提供了一种电路和方法，用于测试边界扫描寄存器位的使能功能，该位用于在IC减少引脚数访问制造测试期间控制1149.1兼容IC的未连接I / O引脚的驱动器，并测试连接到 这些引脚在包含IC的电路板的测试期间，如果引脚无意中短路，则不会引起过大的电流。
-
公开(公告)号：US07158899B2
公开(公告)日：2007-01-02
申请号：US10947189
申请日：2004-09-23
申请人： Stephen K. Sunter , Aubin P. J. Roy
发明人： Stephen K. Sunter , Aubin P. J. Roy
IPC分类号： G01R29/00
CPC分类号： H04L1/205
摘要： A method and circuit for measuring a statistical value of jitter for a data signal having a data rate fD, comprises digitally sampling the data signal at a sampling rate, fS, to produce sampled logic values, where fD/fS is a predetermined non-integer ratio; and analyzing the sampled values to deduce a statistical value of the jitter.
摘要翻译： 一种用于测量具有数据速率f D D D的数据信号的抖动的统计值的方法和电路包括以采样率f S S S取数据信号， 以产生采样的逻辑值，其中f N是一个预定的非整数比; 并分析采样值以推导抖动的统计值。
-
-
-
-
-
-
-
-
-
搜索结果
32 条记录 (耗时 0.017 秒)
