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公开(公告)号：US20050240848A1
公开(公告)日：2005-10-27
申请号：US11109844
申请日：2005-04-20
IPC分类号： G01R31/28 , G01R31/3185
CPC分类号： G01R31/318572
摘要： A masking circuit for selectively masking scan chain inputs and/or outputs during scan testing of an integrated circuit, comprises a mask register having at least two mask register elements for each scan chain to provide a plurality of masking modes; and an input and output mask control circuit for each scan chain, each mask control circuit being connected between a test pattern source and a signature register and between a serial input and a serial output of an associated scan chain and being responsive to mask control data stored in the register elements for configuring the associated scan chain in one of the plurality of masking modes during a scan test of the circuit.
摘要翻译： 一种屏蔽电路，用于在集成电路的扫描测试期间有选择地屏蔽扫描链输入和/或输出，包括屏蔽寄存器，其具有用于每个扫描链的至少两个屏蔽寄存器元件，以提供多个屏蔽模式; 以及用于每个扫描链的输入和输出掩模控制电路，每个掩模控制电路连接在测试图案源和签名寄存器之间，并且连接在相关联的扫描链的串行输入和串行输出之间，并响应于存储的掩码控制数据 在用于在电路的扫描测试期间用于将多个掩模模式中的一个掩模模式中的一个配置为关联的扫描链的寄存器元件中。
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公开(公告)号：US20050240847A1
公开(公告)日：2005-10-27
申请号：US11013319
申请日：2004-12-17
IPC分类号： G01R31/28 , G01R31/3185 , G01R31/319
CPC分类号： G01R31/31858 , G01R31/318552 , G01R31/31922
摘要： A test clock controller for generating a test clock signal for scan chains in integrated circuits having one or more clock domains, comprises a shift clock controller for generating a shift clock signal for use in loading test patterns into scan chains in the clock domains and for unloading a test response patterns from the scan chains and for generating a burst phase signal after loading a test pattern; and a burst clock controller associated with each of one or more clock domains and responsive to a burst phase signal for generating a burst of clock pulses derived from a respective reference clocks and including a first group of burst clock pulses having a selected reduced frequency relative to the reference clock and a second group of burst clock pulses having a frequency corresponding to that of the reference clock.
摘要翻译： 一种测试时钟控制器，用于在具有一个或多个时钟域的集成电路中产生用于扫描链的测试时钟信号，包括移位时钟控制器，用于产生用于将测试模式加载到时钟域中的扫描链中并用于卸载的移位时钟信号 来自扫描链的测试响应模式并且用于在加载测试模式之后产生突发相位信号; 以及突发时钟控制器，其与一个或多个时钟域中的每一个相关联，并且响应于脉冲串相位信号，用于产生从各个参考时钟导出的时钟脉冲串，并且包括相对于相对参考时钟具有选定的降低的频率的第一组脉冲串时钟脉冲 参考时钟和具有与参考时钟的频率对应的频率的第二组突发时钟脉冲。
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公开(公告)号：US5812469A
公开(公告)日：1998-09-22
申请号：US775856
申请日：1996-12-31
摘要： A method of and apparatus for testing multi-port memory performs a shadow read to an adjacent memory cell concurrent with a write operation associated with typical read-write testing. In the presence of a bit wire short or a word wire short, the concurrent read of an adjacent memory cell will cause the value of that cell to be corrupted. The corrupted value is then found by the read-write testing. Consequently, the testing takes no longer than read-write testing. In addition, the testing scheme can be modified for memory with read only ports. An embodiment of the apparatus employs an exclusive OR gate on the least significant bit of the test row address line to generate the shadow read address.
摘要翻译： 用于测试多端口存储器的方法和装置对与典型读写测试相关联的写操作同时执行对相邻存储器单元的影子读取。 在有线短路或字线短路的情况下，相邻存储单元的并发读取将导致该单元的值被破坏。 然后通过读写测试发现损坏的值。 因此，测试不再需要读写测试。 此外，可以使用只读端口对存储器修改测试方案。 该装置的实施例在测试行地址线的最低有效位上采用异或门来产生影子读取地址。
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公开(公告)号：US06510534B1
公开(公告)日：2003-01-21
申请号：US09607128
申请日：2000-06-29
IPC分类号： G01R3128
CPC分类号： G11C29/56012 , G01R31/318552 , G01R31/318563 , G11C29/56 , G11C2029/3202
摘要： A method for at-speed testing high-performance digital systems and circuits having combinational logic and memory elements that may be both scannable and non-scannable is performed by enabling at least two clock pulses during a capture sequence following a shift sequence. The method provides for initialization of any non-scannable memory elements via the scannable memory elements at the beginning of the test before an at-speed test is performed. During initialization, control logic generates a signal to disable the generation of system clock pulses for capture. Instead, only one clock cycle derived from the test clock or a system clock is generated to initialize the non-scannable elements. The number of shift sequences required depends on the maximum number of non-scannable elements that must be traversed between two scannable memory elements. During the same initialization period, the output response analyzer is disabled since unknown data values will present in the stream of data shifted out. A test controller is clocked a test clock and includes a clock generation module for generating shift and capture clocks. The test clock can be an independent and asynchronous clock or derived from the system clock. The test can also be performed by using only the test clock in the case only the test clock is available or for diagnostic and debug purposes.
摘要翻译： 通过在移位序列之后的捕获序列期间能够进行至少两个时钟脉冲来执行用于速度测试高性能数字系统和具有组合逻辑和存储元件可能是可扫描和不可扫描的电路的方法。 该方法提供了在执行速度测试之前在测试开始时经由可扫描存储器元件的任何非可扫描存储器元件的初始化。 在初始化期间，控制逻辑产生一个信号，以禁止生成用于捕获的系统时钟脉冲。 相反，仅产生从测试时钟或系统时钟得到的一个时钟周期来初始化不可扫描元件。 所需的移位序列的数量取决于两个可扫描存储器元件之间必须经过的不可扫描元件的最大数量。 在相同的初始化期间，输出响应分析器被禁用，因为未知数据值将出现在数据流中。 一个测试控制器是一个测试时钟，它包括一个产生移位和捕捉时钟的时钟生成模块。 测试时钟可以是独立的和异步的时钟，也可以从系统时钟导出。 只有在测试时钟可用或用于诊断和调试目的的情况下，也可以仅使用测试时钟进行测试。
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5.发明申请Clocking methodology for at-speed testing of scan circuits with synchronous clocks 有权具有同步时钟的扫描电路的高速测试时钟方法公开(公告)号：US20050240790A1
公开(公告)日：2005-10-27
申请号：US11060407
申请日：2005-02-18
IPC分类号： G01R31/3185 , G06F13/42
CPC分类号： G01R31/31858
摘要： A clocking method for at-speed scan testing for delay defects in cross-domain paths of interacting synchronous clock domains in a scan circuit, each path originating from a source memory element in one of the domains and terminating at a destination memory element in another of the domains and comprises selectively aligning either a capture edge or a launch edge of the clock of each domain with a corresponding edge of at least one other domain of the interacting synchronous clock domains to determine the cross-domain paths to be tested between a source domain and a destination domain; clocking memory elements in each domain at respective domain clock rates to launch signal transitions from source memory elements in source domains; and for each pair of interacting clock domains under test, capturing, in the destination domain, circuit responses to signal transitions launched along paths originating from the source domain and selectively disabling capturing, in the source domain, of circuit responses to signal transitions launched along paths originating from the destination domain.
摘要翻译： 一种用于对扫描电路中相互作用的同步时钟域的跨域路径中的延迟缺陷进行高速扫描测试的时钟方法，每个路径源自一个域中的源存储器元件，并终止于另一个的另一个中的目的地存储器元件 所述域并且包括选择性地将每个域的时钟的捕获边缘或启动边缘与交互的同步时钟域的至少一个其他域的相应边缘对准，以确定要在源域之间测试的跨域路径 和目的域; 以各个域时钟速率在每个域中计时存储器元件以从源域中的源存储器元件启动信号转换; 并且对于正在测试的每对相互作用的时钟域，在目的地域中捕获对源自源域的路径发射的信号转换的电路响应，并且选择性地禁止在源域中捕获沿着路径发射的信号转换的电路响应 源自目的地域。
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6.发明申请公开(公告)号：US20080065929A1
公开(公告)日：2008-03-13
申请号：US11853383
申请日：2007-09-11
IPC分类号： G06F11/16
CPC分类号： G11C29/4401 , G11C29/802 , G11C2029/0401 , G11C2029/4402 , G11C2229/726
摘要： A system for repairing embedded memories on an integrated circuit is disclosed. The system comprises an external Built-In Self-repair Register (BISR) associated with every reparable memory on the circuit. Each BISR is configured to accept a serial input from a daisy chain connection and to generate a serial output to a daisy chain connection, so that a plurality of BISRs are connected in a daisy chain with a fuse box controller. The fuse box controller has no information as to the number, configuration or size of the embedded memories, but determines, upon power up, the length of the daisy chain. With this information, the fuse box controller may perform a corresponding number of serial shift operations to move repair data to and from the BISRs and into and out of a fuse box associated with the controller. Memories having a parallel repair interface are supported by a parallel address bus and enable control signal on the BISR, while those having a serial repair interface are supported by a parallel daisy chain path that may be selectively cycled to shift the contents of the BISR to an internal serial register in the memory. Preferably, each of the BISRs has an associated repair analysis facility having a parallel address bus and enable control signal by which fuse data may be dumped in parallel into the BISR and from there, either uploaded to the fuse box through the controller or downloaded into the memory to effect repairs. Advantageously, pre-designed circuit blocks may provide daisy chain inputs and access ports to effect the inventive system therealong or to permit the circuit block to be bypassed for testing purposes.
摘要翻译： 公开了一种用于在集成电路上修复嵌入式存储器的系统。 该系统包括与电路上的每个可修复存储器相关联的外部内置自修复寄存器（BISR）。 每个BISR被配置为接受来自菊花链连接的串行输入并且产生到菊花链连接的串行输出，使得多个BISR以菊花链连接到保险丝盒控制器。 保险丝盒控制器没有关于嵌入式存储器的数量，配置或尺寸的信息，而是在上电时确定菊花链的长度。 利用该信息，保险丝盒控制器可以执行相应数量的串行移位操作，以将修复数据传送到BISR并从BISR移出并进出与控制器相关联的保险丝盒。 具有并行修复接口的存储器由并行地址总线支持并使能BISR上的控制信号，而具有串行修复接口的存储器由并行菊花链路径支持，该并行菊花链路径可以选择性地循环以将BISR的内容移位到 内部串行寄存器在内存中。 优选地，每个BISR具有相关联的维修分析设备，其具有并行地址总线和启用控制信号，通过该控制信号可以将熔丝数据并行转储到BISR中，并从那里通过控制器上载到保险丝盒或下载到 记忆力进行修复。 有利的是，预先设计的电路块可以提供菊花链输入和访问端口以实现本发明的系统，或者为了测试目的允许绕过电路块。
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7.发明授权Hierarchical design and test method and system, program product embodying the method and integrated circuit produced thereby 有权分层设计和测试方法和系统，程序产品体现了由此产生的方法和集成电路公开(公告)号：US06615392B1
公开(公告)日：2003-09-02
申请号：US09626877
申请日：2000-07-27
申请人： Benoit Nadeau-Dostie , Dwayne Burek , Jean-Francois Cote , Sonny Ngai San Shum , Pierre Girouard , Pierre Gauther , Sai Kennedy Vedantam , Luc Romain , Charles Bernard
发明人： Benoit Nadeau-Dostie , Dwayne Burek , Jean-Francois Cote , Sonny Ngai San Shum , Pierre Girouard , Pierre Gauther , Sai Kennedy Vedantam , Luc Romain , Charles Bernard
IPC分类号： G06F945
CPC分类号： G01R31/318591 , G01R31/318586
摘要： A method for use in the hierarchical design of integrated circuits having at least one module, each the module having functional memory elements and combinational logic, the method comprising reading in a description of the circuit; replacing the description of each functional memory element of the modules with a description of a scannable memory element configurable in scan mode and capture mode; partitioning each module into an internal partition and a peripheral partition by converting the description of selected scannable memory elements into a description of peripheral scannable memory elements which are configurable in an internal test mode, an external test mode and a normal operation mode; modifying the description of modules in the circuit description so as to arrange the memory elements into scan chains in which peripheral and internal scannable memory elements of each module are controlled by an associated module test controller when configured in internal test mode; and peripheral scannable memory elements of each module are controlled by a top-level test controller when configured in an external test mode; and verifying the correct operation of the internal test mode and the external test mode of the circuit.
摘要翻译： 一种在具有至少一个模块的集成电路的分级设计中使用的方法，每个模块具有功能存储元件和组合逻辑，该方法包括读取电路的描述; 用扫描模式和捕获模式可配置的可扫描存储器元件的描述代替模块的每个功能存储元件的描述; 通过将所选择的可扫描存储器元件的描述转换为在内部测试模式，外部测试模式和正常操作模式中可配置的外围可扫描存储器元件的描述，将每个模块分成内部分区和外围分区; 修改电路描述中的模块的描述，以便将存储器元件布置成扫描链，其中当配置在内部测试模式中时，由模块测试控制器控制每个模块的外围和内部可扫描存储元件; 并且当在外部测试模式下配置时，每个模块的外围可扫描存储器元件由顶级测试控制器控制; 并验证电路的内部测试模式和外部测试模式的正确操作。
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公开(公告)号：US20070266278A1
公开(公告)日：2007-11-15
申请号：US11439497
申请日：2006-05-24
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C29/50012 , G11C2029/0401 , G11C2029/3202
摘要： A method and a circuit of testing of a memory interface associated with an embedded memory in a semiconductor circuit involves writing to two memory locations in succession; reading the two memory locations in succession in the same order in which the two memory locations were written; capturing output data from the memory interface; and analyzing captured output data to determine whether said captured output data corresponds to expected data.
摘要翻译： 与半导体电路中的嵌入式存储器相关联的存储器接口的测试方法和电路涉及连续写入两个存储单元; 以写入两个存储器位置的相同顺序连续读取两个存储器位置; 从存储器接口捕获输出数据; 并分析所捕获的输出数据以确定所述捕获的输出数据是否对应于预期数据。
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公开(公告)号：US20050273683A1
公开(公告)日：2005-12-08
申请号：US11144764
申请日：2005-06-06
IPC分类号： G01R31/28 , G01R31/3185 , G06F17/50
CPC分类号： G01R31/318583
摘要： A method of designing a scan testable integrated circuit with embedded test objects for use in scan testing the circuit, comprises compiling a register-transfer level (RTL) circuit description of the circuit into an unmapped circuit description; extracting information from the unmapped circuit description for use in generating and inserting RTL descriptions of test objects into the RTL circuit description and for use in generating and inserting scan chains into the circuit; generating and inserting the RTL descriptions of the test objects into the RTL circuit description to produce a modified RTL circuit description; storing the modified RTL circuit description; synthesizing the modified RTL description into a gate level circuit description of the circuit; and constructing and inserting scan chains into the gate level circuit description according to information extracted from the unmapped circuit description.
摘要翻译： 一种设计具有用于扫描测试电路的嵌入式测试对象的可扫描可测集成电路的方法，包括将电路的寄存器传输电平（RTL）电路描述编译成未映射电路描述; 从未映射电路描述中提取信息，用于生成和插入测试对象的RTL描述到RTL电路描述中，并用于生成和插入扫描链到电路中; 生成并将测试对象的RTL描述插入到RTL电路描述中，以产生修改的RTL电路描述; 存储修改的RTL电路描述; 将修改的RTL描述合成到电路的门级电路描述中; 以及根据从未映射电路描述提取的信息构建并将扫描链插入到门级电路描述中。
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公开(公告)号：US20050047229A1
公开(公告)日：2005-03-03
申请号：US10690594
申请日：2003-10-23
CPC分类号： G11C29/40
摘要： A method and circuit for collecting memory failure information on-chip and unloading the information in real time while performing a test of memory embedded in a circuit comprises, for each column or row of a memory under test, testing each memory location of the column or row according to a memory test algorithm under control of a first clock, selectively generating a failure summary on-circuit while testing each column or row of the memory; and transferring the failure summary from the circuit under control of a second clock within the time required to test the next column or row, if any, of the memory under test.
摘要翻译： 一种用于在执行嵌入在电路中的存储器的测试的同时实时地收集片上存储器故障信息并实时卸载信息的方法和电路包括：对于被测存储器的每一列或一行，测试该列的每个存储器位置或 根据在第一时钟的控制下的存储器测试算法，在测试存储器的每个列或行的同时选择性地生成电路故障摘要; 以及在测试所测试的存储器的下一个列或行（如果有的话）所需的时间内从第二时钟的控制下传送来自电路的故障摘要。
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