公开(公告)号：US20060220704A1

公开(公告)日：2006-10-05

申请号：US11092506

申请日：2005-03-29

申请人： Douglas Butler

发明人： Douglas Butler

IPC分类号： H03B1/00

CPC分类号： G11C7/1078 ,  G11C7/1084

摘要： A high-speed, low-power input buffer for an integrated circuit device in which the input voltage (VIN) is coupled to both a pull-up and a pull-down transistor. In accordance with a specific embodiment, the input buffer utilizes a reference voltage input (VREF) during a calibration phase of operation but not when in an active operational mode. A maximum level of through current is supplied when VIN=VREF with lower levels of through current at all other VIN voltages. In an integrated circuit device incorporating an input buffer as disclosed, two (or more) input buffers may be utilized per device input pin.

公开(公告)号：US20070058468A1

公开(公告)日：2007-03-15

申请号：US11224541

申请日：2005-09-12

申请人： Douglas Butler

发明人： Douglas Butler

IPC分类号： G11C7/02

CPC分类号： G11C11/4097 ,  G11C7/02 ,  G11C7/18 ,  G11C2207/104

摘要： A shielded bitline architecture for DRAM memories and integrated circuit devices incorporating embedded DRAM is disclosed herein which comprises a shared sense amplifier, folded bitline array using a bitline from an adjacent, non-active subarray as a reference for a bitline in an active array.

摘要翻译： 本文公开了一种用于DRAM存储器和集成嵌入式DRAM的集成电路器件的屏蔽位线架构，其包括共享读出放大器，使用来自相邻非活动子阵列的位线的折叠位线阵列作为有源阵列中的位线的参考。

公开(公告)号：US20070085152A1

公开(公告)日：2007-04-19

申请号：US11250822

申请日：2005-10-14

申请人： Douglas Butler ,  Chia-Shun Hsiao ,  Jung-Wu Chien ,  Chih-Hsun Chu

发明人： Douglas Butler ,  Chia-Shun Hsiao ,  Jung-Wu Chien ,  Chih-Hsun Chu

IPC分类号： H01L29/76

CPC分类号： H01L27/10867 ,  H01L27/0207

摘要： A reduced area dynamic random access memory (DRAM) cell and method for fabricating the same wherein the cell occupies an area smaller than one photolithography pitch by two photolithography pitches through the formation of sidewall spacers along a first pattern to define a first portion of the active region of the memory cell and a second orthogonally oriented pattern to define a second portion of the active region of the memory cell thereby creating a ladder shaped active region for a column of the memory cells.

摘要翻译： 一种缩小面积动态随机存取存储器（DRAM）单元及其制造方法，其中通过沿着第一图案形成侧壁间隔物，通过两个光刻间距占据小于一个光刻间距的区域，以限定活动的第一部分 存储单元的区域和第二正交定向图案，以限定存储单元的有源区域的第二部分，从而为存储单元的列创建梯形有源区域。

公开(公告)号：US20070091691A1

公开(公告)日：2007-04-26

申请号：US11257610

申请日：2005-10-25

申请人： Jon Faue ,  Van Butler

发明人： Jon Faue ,  Van Butler

IPC分类号： G11C7/10

CPC分类号： G06F5/06

摘要： A circuit provides the widest possible window for capturing data and preventing run-through in a FIFO register. The FIFO register includes two registers per I/O. Two FIFO input clocks are used, one for each FIFO register. When one FIFO clock is active, the other is automatically disabled. Initially, the circuit is reset such that one clock is active, and the other disabled. Upon receiving a valid READ command, a shift chain attached to the FICLK that is currently low begins counting the clock cycles. This eventually determines when the FICLK that is currently low can be enabled. The final enable is dependent upon the turning off the FICLK that is currently high. The FICLK that is enabled during the reset turns off a fixed delay after the falling edge of the YCLK associated with the READ command.

摘要翻译： 一个电路提供了最广泛的窗口，用于捕获数据并防止FIFO寄存器中的溢出。 FIFO寄存器每个I / O包含两个寄存器。 使用两个FIFO输入时钟，每个FIFO寄存器一个。 当一个FIFO时钟激活时，另一个FIFO被自动禁止。 最初，电路复位，使得一个时钟有效，另一个被禁止。 当接收到有效的READ命令时，附加到FICLK当前为低电平的移位链开始计数时钟周期。 这最终确定何时可以启用当前为低电平的FICLK。 最终启用取决于关闭当前高的FICLK。 在复位期间使能的FICLK在与READ命令相关联的YCLK的下降沿之后关闭固定延迟。