公开(公告)号：US20100284701A1

公开(公告)日：2010-11-11

申请号：US11938754

申请日：2007-11-12

申请人： Christopher Lin ,  Mark Summa ,  Martin Williams ,  Douglas Butler ,  Peter Wigley

发明人： Christopher Lin ,  Mark Summa ,  Martin Williams ,  Douglas Butler ,  Peter Wigley

IPC分类号： H04B10/00

CPC分类号： H04B10/2513

摘要： One embodiment sets forth a technique for measuring chromatic dispersion using reference signals within the operational range of amplifiers used to refresh data signals. One red/blue laser pair in the transmission node is used for measuring dispersion and chromatic dispersion compensation is added at each line node in the system. Since reference and data signals propagate through each amplifier, the reference signals used to measure chromatic dispersion receive the same dispersion compensation (and will have the same residual dispersion) as the data signals. Therefore, any residual dispersion in the data signals will manifest itself in downstream dispersion measurements and, thus, can be corrected. The tunable dispersion compensator in each line node may be set to compensate for the measured dispersion, thereby compensating for both the chromatic dispersion of the link connecting the current node to the prior node and any uncorrected residual dispersion from prior nodes.

摘要翻译： 一个实施例提出了使用用于刷新数据信号的放大器的操作范围内的参考信号来测量色散的技术。 传输节点中的一个红/蓝激光对用于测量色散，并且在系统中的每个线路节点处添加色散补偿。 由于参考和数据信号通过每个放大器传播，用于测量色散的参考信号将接收与数据信号相同的色散补偿（并将具有相同的残留色散）。 因此，数据信号中的任何残留色散将在下游色散测量中显现，因此可以被校正。 每个线路节点中的可调谐色散补偿器可以被设置为补偿测量的色散，由此补偿连接当前节点到先前节点的链路的色散和来自先前节点的任何未校正的残余色散。

公开(公告)号：US20060005053A1

公开(公告)日：2006-01-05

申请号：US10881767

申请日：2004-06-30

申请人： Oscar Jones ,  Douglas Butler ,  Michael Parris

发明人： Oscar Jones ,  Douglas Butler ,  Michael Parris

IPC分类号： G06F1/26

CPC分类号： G06F12/0804 ,  G06F1/3203 ,  G06F1/3275 ,  G06F2212/1028 ,  G06F2212/3042 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

摘要： A cache and tag power-down function during low-power data retention standby mode technique for cached integrated circuit memory devices, in particular cached dynamic random access memory (DRAM) and cached static random access memory (SRAM), wherein the data in the cache is written back from cache to the main memory arrays (write-back operation) when power-down is entered such that the cache, tag and much of the cache control logic can be powered-down during power-down standby mode. If a DRAM cache is used, the refresh cycles can be inhibited to the DRAM cache, since it has been powered-down, so that additional power savings can be realized during self-refresh power-down standby. When power-down standby is exited, the cache operations are enabled as soon as the cache, tag and control circuitry are powered-up and a clear tag sequence is executed.

摘要翻译： 用于缓存的集成电路存储器件（特别是缓存的动态随机存取存储器（DRAM））和高速缓存的静态随机存取存储器（SRAM）的低功率数据保持待机模式技术中的高速缓存和标签掉电功能，其中高速缓存中的数据 在输入掉电时，从高速缓存写入主存储器阵列（回写操作），使得高速缓存，标签和大部分高速缓存控制逻辑在掉电待机模式下可以掉电。 如果使用DRAM高速缓存，则可以禁止刷新周期到DRAM高速缓存，因为它已经掉电，从而在自刷新掉电待机期间可以实现额外的功率节省。 当退出备用电源时，一旦高速缓存，标签和控制电路通电并且执行了清晰的标签序列，就启用高速缓存操作。

公开(公告)号：US20050289293A1

公开(公告)日：2005-12-29

申请号：US10878802

申请日：2004-06-28

申请人： Michael Parris ,  Douglas Butler

发明人： Michael Parris ,  Douglas Butler

IPC分类号： G06F12/00 ,  G11C8/16 ,  G11C11/405 ,  G11C11/406

CPC分类号： G11C11/405 ,  G11C8/16 ,  G11C11/406 ,  G11C11/40603

摘要： A dual-port memory substantially eliminates noise problems associated with the staggered methods of operation. The first and second word lines of a dual-port memory cell are simultaneously activated, such that all four bit lines associated with the cell also move at the same time. The dual-port memory uses simple control logic circuitry without the need for additional external control signals. There are no lock-out times or write restrictions with the method of the present invention. The dual-port memory of the present invention includes a method for hiding refresh, and a method for increasing operating speed.

摘要翻译： 双端口存储器基本上消除了与交错操作方法相关联的噪声问题。 同时激活双端口存储器单元的第一和第二字线，使得与单元相关联的所有四个位线也同时移动。 双端口存储器使用简单的控制逻辑电路，而不需要额外的外部控制信号。 通过本发明的方法，没有锁定时间或写入限制。 本发明的双端口存储器包括用于隐藏刷新的方法，以及用于提高操作速度的方法。

公开(公告)号：US5385634A

公开(公告)日：1995-01-31

申请号：US43569

申请日：1993-04-07

申请人： Douglas Butler ,  E. Henry Stevens ,  Richard A. Bailey ,  Thomas C. Taylor

发明人： Douglas Butler ,  E. Henry Stevens ,  Richard A. Bailey ,  Thomas C. Taylor

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L23/485 ,  H01L29/78 ,  H01L21/00

CPC分类号： H01L21/76897 ,  H01L21/28512 ,  H01L21/76804 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S438/97

摘要： In fabricating a contact window to source/drain electrode next to a gate electrode of an integrated circuit: (1) establishing a structure with a window over the source/drain region next to the gate electrode; (2) establishing a region of titanium silicide over the source/drain electrode and establishing a titanium nitride layer over the window and gate electrode; (3) establishing a layer of silicon nitride over the titanium nitride layer; (4) patterning the silicon nitride layer; (5) using the patterned silicon nitride layer as a mask to pattern the titanium nitride layer; (6) adding another silicon nitride layer to seal the gate electrode where it is not protected by titanium nitride; (7) opening a window over the electrode by an anisotropic etch; (8) widening the window with an isotropic etch, using the silicon nitride and titanium nitride as a protective barrier; and (9) adding contact material in said windows.

摘要翻译： 在制造与集成电路的栅电极相邻的源极/漏电极的接触窗口时：（1）在栅电极旁边的源极/漏极区域上建立具有窗口的结构; （2）在源/漏电极上建立硅化钛区域，并在窗口和栅电极上建立氮化钛层; （3）在氮化钛层上建立氮化硅层; （4）构图氮化硅层; （5）使用图案化氮化硅层作为掩模来图案化氮化钛层; （6）添加另一个氮化硅层以密封其不受氮化钛保护的栅电极; （7）通过各向异性蚀刻在电极上打开窗口; （8）使用氮化硅和氮化钛作为保护屏障，用各向同性蚀刻来加宽窗口; 和（9）在所述窗口中添加接触材料。

公开(公告)号：US5043790A

公开(公告)日：1991-08-27

申请号：US505242

申请日：1990-04-05

申请人： Douglas Butler

发明人： Douglas Butler

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L23/485 ,  H01L29/78

CPC分类号： H01L21/76897 ,  H01L21/28512 ,  H01L21/76804 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S438/97

摘要： In a contact structure to a source/drain region (28) nearby a gate electrode (22), a contact sidewall through a thick dielectric is laterally displaced away from the S/D region to widen the contact; the contact sidewall is located over the gate electrode. Titanium silicide (34) is located upon the S/D. A remnant (36a) of a (conductive) TiN layer overlies the silicide and rises up along the sidewall of gate electrode insulation and onto insulation atop the gate electrode, and is insulated from the gate electrode thereby. A further nitride, preferably Si.sub.3 N.sub.4, is located under the thick dielectric and over part of the gate electrode insulation. The Si.sub.3 N.sub.4 adjoins the TiN to enclose the top and sides of the gate electrode with nitride. The bottom of the contact is formed by one nitride at some locations and by the other nitride at other locations. The contact sidewall through the thick dielectric preferably overlies the Si.sub.3 N.sub.4 but not the TiN. The TiN is effective as a dry etch stop and a wet etch stop, and the silicon nitride is effective as an isotropic etch stop. The conductive nitride is wholly contained within the contact, and the further nitride extends beyond said contact.

公开(公告)号：US20070121414A1

公开(公告)日：2007-05-31

申请号：US11625744

申请日：2007-01-22

申请人： Douglas Butler

发明人： Douglas Butler

IPC分类号： G11C7/02

CPC分类号： G11C11/4097 ,  G11C7/02 ,  G11C7/18 ,  G11C2207/104

摘要： A shielded bitline architecture for DRAM memories and integrated circuit devices incorporating embedded DRAM is disclosed herein which comprises a shared sense amplifier, folded bitline array using a bitline from an adjacent, non-active subarray as a reference for a bitline in an active array.

摘要翻译： 本文公开了一种用于DRAM存储器和集成嵌入式DRAM的集成电路器件的屏蔽位线架构，其包括共享读出放大器，使用来自相邻非活动子阵列的位线的折叠位线阵列作为有源阵列中的位线的参考。

公开(公告)号：US20060220704A1

公开(公告)日：2006-10-05

申请号：US11092506

申请日：2005-03-29

申请人： Douglas Butler

发明人： Douglas Butler

IPC分类号： H03B1/00

CPC分类号： G11C7/1078 ,  G11C7/1084

摘要： A high-speed, low-power input buffer for an integrated circuit device in which the input voltage (VIN) is coupled to both a pull-up and a pull-down transistor. In accordance with a specific embodiment, the input buffer utilizes a reference voltage input (VREF) during a calibration phase of operation but not when in an active operational mode. A maximum level of through current is supplied when VIN=VREF with lower levels of through current at all other VIN voltages. In an integrated circuit device incorporating an input buffer as disclosed, two (or more) input buffers may be utilized per device input pin.

公开(公告)号：US20050286339A1

公开(公告)日：2005-12-29

申请号：US10878925

申请日：2004-06-28

申请人： Michael C. Parris ,  Oscar Frederick Jones ,  Douglas Butler

发明人： Michael C. Parris ,  Oscar Frederick Jones ,  Douglas Butler

IPC分类号： G11C8/00 ,  G11C11/406

CPC分类号： G11C11/406 ,  G11C5/144 ,  G11C11/40626 ,  G11C2211/4067 ,  G11C2211/4068

摘要： A low power Sleep Mode operation technique for dynamic random access (DRAM) devices and integrated circuit devices incorporating embedded DRAM. By counting clock (CLK) cycles in accordance with the technique disclosed, refresh time (tREF) does not vary with all possible process corners, voltages and temperatures (PVT) since the clock signal exhibits a steady frequency over PVT applied to the DRAM and an internal timer placed on chip will vary directly with these parameters. After entering Sleep Mode, the main internal clock signal is inhibited from propagating around the device chip and, at this time, much of the associated circuitry can be power-gated to conserve power, typically with signals that have a boosted level to provide a negative gate-to-source voltage (VGS) on the power-gating transistors.

摘要翻译： 一种用于动态随机存取（DRAM）器件和集成嵌入式DRAM的集成电路器件的低功耗睡眠模式操作技术。 通过根据所公开的技术对时钟（CLK）周期进行计数，由于时钟信号表现出稳定的频率，因此所有可能的处理角，电压和温度（PVT）都不会改变刷新时间（t REF REF） 通过施加到DRAM的PVT和放置在芯片上的内部定时器将随着这些参数而变化。 在进入睡眠模式之后，禁止主内部时钟信号在器件芯片周围传播，此时，大部分相关电路可以通过电源门控来节省功耗，通常使用具有提升电平的信号来提供负极 电源门控晶体管上的栅极至源极电压（V SUB）。

公开(公告)号：US20070058468A1

公开(公告)日：2007-03-15

申请号：US11224541

申请日：2005-09-12

申请人： Douglas Butler

发明人： Douglas Butler

IPC分类号： G11C7/02

CPC分类号： G11C11/4097 ,  G11C7/02 ,  G11C7/18 ,  G11C2207/104

摘要： A shielded bitline architecture for DRAM memories and integrated circuit devices incorporating embedded DRAM is disclosed herein which comprises a shared sense amplifier, folded bitline array using a bitline from an adjacent, non-active subarray as a reference for a bitline in an active array.

摘要翻译： 本文公开了一种用于DRAM存储器和集成嵌入式DRAM的集成电路器件的屏蔽位线架构，其包括共享读出放大器，使用来自相邻非活动子阵列的位线的折叠位线阵列作为有源阵列中的位线的参考。

公开(公告)号：US20060190676A1

公开(公告)日：2006-08-24

申请号：US11064354

申请日：2005-02-23

申请人： Douglas Butler ,  Oscar Jones ,  Michael Parris ,  Kim Hardee

发明人： Douglas Butler ,  Oscar Jones ,  Michael Parris ,  Kim Hardee

IPC分类号： G06F13/28

CPC分类号： G06F12/0804 ,  G11C11/406 ,  G11C11/40607 ,  G11C11/4076

摘要： A high-speed, static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate data read and write registers and tag blocks. The inclusion of separate data read and write registers allows the device to effectively operate at a cycle time limited only by the DRAM subarray cycle time. Further, the inclusion of two tag blocks allows one to be accessed with an externally supplied address and the other to be accessed with a write-back address, thus eliminating the requirement for a single tag to execute two read-modify write cycles in one DRAM cycle time.