SYSTEM AND METHOD FOR DISPLAY SYNCHRONIZATION

    公开(公告)号:US20240012518A1

    公开(公告)日:2024-01-11

    申请号:US18459249

    申请日:2023-08-31

    Abstract: A method of operating a display includes performing a non-synchronized touch scan pattern on a display with a controller coupled to the display. The non-synchronized touch scan pattern schedules touch scans independent of a refresh rate of the display. Upon the controller detecting a first synchronization pulse from a display controller coupled to the controller and the display, a first pulse-checking timer is started. Upon detecting a second synchronization pulse from the display controller and before the first pulse-checking timer expires, a first display refresh rate for the display is obtained from an interval between the first synchronization pulse and the second synchronization pulse. A synchronized touch scan pattern is performed with the controller, and is scheduled to avoid touch scans coinciding with refreshes of the display performed at the first display refresh rate.

    TOUCHSCREEN
    3.
    发明公开
    TOUCHSCREEN 审中-公开

    公开(公告)号:US20230266845A1

    公开(公告)日:2023-08-24

    申请号:US17677119

    申请日:2022-02-22

    CPC classification number: G06F3/0418 G06F3/0446 G06F3/0412 G06F3/0447

    Abstract: A method for operating an electronic device includes detecting, by a touchscreen controller, a touch point on a touchscreen; determining, by the touchscreen controller, coordinates of the touch point; scaling, by the touchscreen controller, up the coordinates of the touch point to obtain scaled up coordinates by overwriting a reserved portion of a touch event protocol with additional information corresponding to the coordinates of the touch point; reporting, by the touchscreen controller, the scaled up coordinates of the touch point to an application processor; and determining, by the application processor, the coordinates of the touch point with an increased resolution by converting the scaled up coordinates into a floating point value.

    Debugging support unit for microprocessor

    公开(公告)号:US10970192B2

    公开(公告)日:2021-04-06

    申请号:US16368742

    申请日:2019-03-28

    Abstract: A debug-enabled processing device includes a processor, a communication transceiver circuit, and a debug support unit. The debug support unit has a plurality of dedicated debug registers to facilitate debugging a software program under execution by the processor. One of the plurality of debug registers is a control register having at least four bits, which are used to enable/disable a plurality of debugging operations. Others of the debug registers include a set of index registers that may be configured to pass data to and from the processor.

    TOUCH MOTION TRACKING AND REPORTING TECHNIQUE FOR SLOW TOUCH MOVEMENTS

    公开(公告)号:US20190113999A1

    公开(公告)日:2019-04-18

    申请号:US15803054

    申请日:2017-11-03

    Abstract: A method includes upon sensing a touch to a first location on a touch display, reporting first coordinates of the touch. After sensing movement of the touch along a first path from the first location to a second location more than a tolerance distance away, intermediate coordinates of the touch along the first path that are not more than a cutoff distance away are reported such that there is a first gap between a last reported intermediate coordinate and the second location. After sensing movement of the touch along a second path from the second location to a third location more, second coordinates of the touch are reported, the second reported coordinates of the touch being a point along the first path that is calculated by subtracting the first gap from a distance between the first location and the third location, and then adding a first compensation difference thereto.

    Driving circuit for power switch
    8.
    发明授权

    公开(公告)号:US09813051B2

    公开(公告)日:2017-11-07

    申请号:US15052170

    申请日:2016-02-24

    Inventor: Zhenghao Cui

    CPC classification number: H03K17/04106 H03K17/165

    Abstract: An electronic circuit is for switching a power transistor having a drain coupled to a drain node, a source coupled to a lower voltage supply, and a gate coupled to a gate node. The electronic circuit includes first current generation circuitry to generate a first current to flow into the gate node in response to assertion off an ON signal, the first current being substantially constant. Second current generation circuitry generates a second current to flow into the gate node in response to deassertion of an OFF signal, the second current being inversely proportional to a gate to source voltage of the power transistor. First comparison circuitry compares a drain voltage at the drain node to a reference voltage, and activates third current generation circuitry to generate a third current to flow into the gate node when the drain voltage is less than the reference voltage.

    MAC and TCP coordination approach for performance improvement in IEEE 802.16e mobile broadband access systems
    9.
    发明授权
    MAC and TCP coordination approach for performance improvement in IEEE 802.16e mobile broadband access systems 有权
    MAC和TCP协调方法,用于IEEE 802.16e移动宽带接入系统的性能改进

    公开(公告)号:US08681742B2

    公开(公告)日:2014-03-25

    申请号:US13167228

    申请日:2011-06-23

    CPC classification number: H04L1/187 H04L1/1607 H04W36/0011

    Abstract: A mobile device includes a communications protocol stack including a MAC layer and TCP layer separated by an IP layer. A cross-layer coordination module parallel to the communications protocol stack is coupled to both the MAC layer and TCP layer. The MAC layer generates a message sent to the cross-layer coordination module indicating that the mobile device is about to engage in a communications handover from a first base station to a second base station. The cross-layer coordination module passes handover information to the TCP layer so as to inform the TCP layer of the communications handover. If the mobile device is operating as a TCP sender, the TCP layer freezes its connection and state during the communications handover. If the mobile device is operating as a TCP receiver, the TCP layer sends a TCP ACK message to a TCP sender having an advertised window size set to a zero value so as to cause the TCP sender to freeze a connection and state during communications handover.

    Abstract translation: 移动设备包括通信协议栈,其包括由IP层分隔的MAC层和TCP层。 与通信协议栈并行的跨层协调模块耦合到MAC层和TCP层。 MAC层产生发送到跨层协调模块的消息,指示移动设备即将从第一基站到第二基站进行通信切换。 跨层协调模块将切换信息传递给TCP层,以通知TCP层通信切换。 如果移动设备作为TCP发送者运行,则TCP层在通信切换期间冻结其连接和状态。 如果移动设备作为TCP接收器操作,则TCP层向广播窗口大小设置为零值的TCP发送器发送TCP ACK消息,以使TCP发送者在通信切换期间冻结连接和状态。

    Register renaming system using multi-bank physical register mapping table and method thereof
    10.
    发明授权
    Register renaming system using multi-bank physical register mapping table and method thereof 有权
    使用多库物理寄存器映射表及其方法的注册重命名系统

    公开(公告)号:US08583901B2

    公开(公告)日:2013-11-12

    申请号:US12700638

    申请日:2010-02-04

    CPC classification number: G06F9/3012 G06F9/384

    Abstract: Embodiments of a processor architecture utilizing multi-bank implementation of physical register mapping table are provided. A register renaming system to correlate architectural registers to physical registers includes a physical register mapping table and a renaming logic. The physical register mapping table has a plurality of entries each indicative of a state of a respective physical register. The mapping table has a plurality of non-overlapping sections each of which having respective entries of the mapping table. The renaming logic is coupled to search a number of the sections of the mapping table in parallel to identify entries that indicate the respective physical registers have a first state. The renaming logic selectively correlates each of a plurality of architectural registers to a respective physical register identified as being in the first state. Methods of utilizing the multi-bank implementation of physical register mapping table are also provided.

    Abstract translation: 提供了利用多库实现物理寄存器映射表的处理器架构的实施例。 将结构寄存器与物理寄存器相关联的寄存器重命名系统包括物理寄存器映射表和重命名逻辑。 物理寄存器映射表具有多个表示每个物理寄存器的状态的条目。 映射表具有多个非重叠部分,每个部分具有映射表的相应条目。 重命名逻辑被耦合以并行地搜索映射表的多个部分以识别指示相应物理寄存器具有第一状态的条目。 重命名逻辑选择性地将多个体系结构寄存器中的每一个相关于被识别为处于第一状态的相应物理寄存器。 还提供了利用多库实现物理寄存器映射表的方法。

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