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    High speed fluidic devices
    1.
    发明授权
    High speed fluidic devices 失效
    高速流体装置

    公开(公告)号：US3825739A

    公开(公告)日：1974-07-23

    申请号：US7290270

    申请日：1970-09-16

    申请人： MARTIN MARIETTA CORP

    发明人： RICHARDS E ,  DEPPERMAN W

    IPC分类号： F15C1/08 ,  F15C5/00 ,  G06D1/10

    CPC分类号： G06D1/10 ,  F15C1/08 ,  F15C5/00

    摘要： This invention relates to a binary accumulator stage consisting of pure fluid bistable and OR-NOR elements. The stage is joined with other similar stages to form a binary accumulator. Each stage sums an input value, a carry-in value supplied by a previous stage, and an addend value present in the addend register. An output signal and a carry-out signal are generated by each stage, the carry-out signal being fed to the succeeding stage as a carry-in signal.

    摘要翻译： 本发明涉及由纯液体双稳态和OR-NOR元件组成的二元累加器级。 该阶段与其他类似的阶段结合形成一个二进制累加器。 每个级将输入值，由前一级提供的进位值和加数寄存器中存在的加数值相加。 输出信号和进位输出信号由各级产生，进位信号作为进位信号被馈送到后级。

    Fluidic adder-subtracter utilizing threshold logic
    4.
    发明授权
    Fluidic adder-subtracter utilizing threshold logic 失效
    流体加料器利用阈值逻辑

    公开(公告)号：US3698632A

    公开(公告)日：1972-10-17

    申请号：US3698632D

    申请日：1969-12-02

    申请人： CORNING GLASS WORKS

    发明人： ECKERLIN HERBERT M

    IPC分类号： F15C1/14 ,  G06D1/10 ,  G06M1/00

    CPC分类号： F15C1/14 ,  G06D1/10

    摘要： A fluidic adder-subtracter stage utilizing the principles of threshold logic. This circuit consists of two fluidic threshold gates, a first having three inputs and a second having four inputs. The two bits from the given order and the carry bit or the borrow bit from the previous order are coupled to the three first gate inputs and three of the second gate inputs. An output from the first gate is coupled to the fourth input of the second gate. When the stage is utilized as an adder the first gate provides a carry out signal and the second gate provides a sum signal. When it is used as a subtracter, the first gate provides a borrow out signal and the second gate provides a difference signal.