公开(公告)号：US20240061649A1

公开(公告)日：2024-02-22

申请号：US18306686

申请日：2023-04-25

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Soon-Wan KWON ,  Seok Ju YUN ,  Seungchul JUNG

IPC分类号： G06F7/544 ,  G06F7/527 ,  G11C7/10

CPC分类号： G06F7/5443 ,  G06F7/5277 ,  G11C7/1069

摘要： An in-memory computing (IMC) processor includes IMC macros, and includes a static random access memory (SRAM) IMC device including the plurality of IMC macros, and configured to perform a multiply and accumulate (MAC) operation between input data and first weight data of a first weight map applied to a first of IMC macros in a first direction in which an input feature map including the input data is written to the first IMC macro, and a two-dimensional (2D) shift accumulator configured to perform a shift operation on partial sums corresponding to respective MAC operation results of the IMC macros and accumulate a result of the shift operation.

公开(公告)号：US2429228A

公开(公告)日：1947-10-21

申请号：US59870245

申请日：1945-06-11

申请人： RCA CORP

发明人： HERBST PHILIP J

IPC分类号： G06F7/52

CPC分类号： G06F7/5277 ,  G06F7/525

公开(公告)号：US3582634A

公开(公告)日：1971-06-01

申请号：US3582634D

申请日：1968-10-15

申请人： STROMBERG CARLSON CORP

发明人： BARTLETT WILLIAM F

IPC分类号： G06F7/52 ,  G06F7/39

CPC分类号： G06F7/5277

摘要： A binary number represented by time spaced electrical pulses and intervals is multiplied by a binary multiplier represented by electrical conditions at plural spaced-apart terminals. The multiplicand is multiplied sequentially by the successive digits of the multiplier to produce partial products. The partial products are applied to binary adders and cumulatively added to produce a final product. The multiplications are done by selectively inhibiting and partially enabling gates at the inputs to the adders in accordance with the digits of the multiplier. The multiplicand signals are applied through a shift register to the gates in sequence. The adders are arranged for serial addition and in cascade.

公开(公告)号：US2941720A

公开(公告)日：1960-06-21

申请号：US75716058

申请日：1958-08-25

申请人： MARSHALL JR BYRON O ,  DILLON JOHN D

发明人： MARSHALL JR BYRON O ,  DILLON JOHN D

IPC分类号： G06F7/52 ,  G06F7/60

CPC分类号： G06F7/5277 ,  G06F7/5318 ,  G06F7/607

公开(公告)号：US6167421A

公开(公告)日：2000-12-26

申请号：US57571

申请日：1998-04-09

申请人： Woodrow Meeker ,  Andrew P. Abercrombie ,  Michele D. Van Dyke-Lewis

发明人： Woodrow Meeker ,  Andrew P. Abercrombie ,  Michele D. Van Dyke-Lewis

IPC分类号： G06F7/52

CPC分类号： G06F7/5277 ,  G06F7/5334

摘要： Bit-serial processors quickly multiply multiple-bit operands using significantly fewer clock cycles as compared to conventional bit-serial implementations. Exemplary embodiments process groups of operand bits simultaneously to provide the significant speed increases. Advantageously, however, the exemplary embodiments utilize logic and memory architectures which are fully compatible with, and fully useful for, conventional bit-serial applications, and the embodiments thus provide fast multiple-bit multiplications while at the same time providing all of the advantages typically associated with conventional bit-serial processors.

摘要翻译： 与传统的位串行实现相比，位串行处理器可以快速地将多位操作数乘以显着更少的时钟周期。 示例性实施例同时处理操作数位组以提供显着的速度增加。 然而，有利的是，示例性实施例利用与传统的比特串行应用完全兼容并且完全有用的逻辑和存储器体系结构，并且实施例因此提供快速的多比特乘法，同时提供所有优点 与传统的位串行处理器相关联。

公开(公告)号：US3885141A

公开(公告)日：1975-05-20

申请号：US44006774

申请日：1974-02-06

申请人： BELL TELEPHONE LABOR INC

发明人： KIEBURTZ ROBERT BRUCE

IPC分类号： G06F7/52 ,  G06F7/54

CPC分类号： G06F7/5277 ,  G06F7/49963 ,  G06F2207/3884

摘要： A serial digital multiplier includes m identical cascaded stages for generating the rounded product of an n-bit binary data word and an m-bit binary coefficient word. The multiplier further includes means for applying a logic 1 signal to the first stage to effect rounding of the final product at the output of the multiplier.

摘要翻译： 串行数字乘法器包括m个相同的级联级，用于产生n位二进制数据字和m位二进制系数字的舍入乘积。 乘法器还包括用于将逻辑1信号施加到第一级以在乘法器的输出处实现最终乘积舍入的装置。

公开(公告)号：US3805043A

公开(公告)日：1974-04-16

申请号：US29656272

申请日：1972-10-11

申请人： BELL TELEPHONE LABOR INC

发明人： CLARY J

IPC分类号： G06F7/52 ,  G06F7/54

CPC分类号： G06F7/5277 ,  G06F2207/3884

摘要： A serial-parallel two''s complement binary multiplier circuit featuring a tightly clocked arrangement facilitating the formation of a product signal in an interval of duration shorter than the arrival interval for a serial multiplicand word. Hence, the multiplier circuit is capable of processing butted-word inputs in real time with only minor constraints on word formats. The multiplication algorithm features a pairwise summation of partial products on a least-significant-bit-first basis which gives rise to a tree-like structure of substantially identical circuit modules. Negative multiplicands are treated using a postmultiplication correction circuit.

摘要翻译： 一种串并联二进制补码二进制电路，具有紧密的时钟配置，便于在一个持续时间短于串行被乘数字的到达间隔的时间间隔内形成产品信号。 因此，乘法器电路能够实时处理对称字输入，对字格式只有很小的限制。 乘法算法具有基于最低有效位优先的部分乘积的成对求和，其产生基本相同的电路模块的树状结构。 负乘法器使用后乘法校正电路进行处理。

公开(公告)号：US3034722A

公开(公告)日：1962-05-15

申请号：US75423058

申请日：1958-08-11

申请人： NAT RES DEV

发明人： BENTLEY STRINGER JOHN

IPC分类号： G06F7/52

CPC分类号： G06F7/5277 ,  G06F2207/386

公开(公告)号：US20230297336A1

公开(公告)日：2023-09-21

申请号：US17698166

申请日：2022-03-18

申请人： Arm Limited

发明人： Nicholas Andrew PFISTER ,  David Raymond LUTZ ,  Harsha VALSARAJU

IPC分类号： G06F7/53 ,  G06F7/527 ,  H03K19/017 ,  H03K19/20

CPC分类号： G06F7/5324 ,  G06F7/5277 ,  H03K19/01728 ,  H03K19/20

摘要： A data processing apparatus is provided. An A×B multiplier array has a group of logic gates clocked by a first clock signal, where A and B are both integers. A C×D multiplier array, separate from the A×B multiplier array, has second group of logic gates clocked by a second clock signal, where C and D are both integers. Addition circuitry performs an addition operation between a first at least partial product produced by the A×B multiplier array and a second at least partial product produced by the C×D multiplier array.

公开(公告)号：US3959639A

公开(公告)日：1976-05-25

申请号：US505495

申请日：1974-09-12

申请人： Wolfgang Koethmann

发明人： Wolfgang Koethmann

IPC分类号： G06F7/52

CPC分类号： G06F7/5277

摘要： In the case of a calculating unit for serial multiplication of a binary multiplicand with a binary multiplier, the multiplicand is inserted into a shift register in serial form. The development of the product is achieved by suitably providing change-over switches at positions of the shift register conforming to binary ones of the multiplier. The product is filled with the sign digit to the required number of digits by the change-over switches which then connect the output with a sign register.

摘要翻译： 在二进制乘法器与二进制乘法器的串行乘法的计算单元的情况下，被乘数以串行形式插入到移位寄存器中。 通过在符合乘法器的二进制位移的移位寄存器的位置处适当地提供转换开关来实现产品的开发。 产品通过转换开关将符号数字填充到所需数量的数字，然后将输出与符号寄存器连接。