公开(公告)号：US09407236B2

公开(公告)日：2016-08-02

申请号：US14182391

申请日：2014-02-18

申请人： KAPIK INC.

发明人： William Martin Snelgrove

IPC分类号： G06F17/10 ,  H03H9/46 ,  H03H17/02

CPC分类号： H03H9/46 ,  H03H17/0219 ,  H03H17/0288

摘要： A system and method for processing a signal with a filter employing FIR and/or IIR elements. The required controller function is decomposed into primary FIR and/or IIR elements and a compensation filter is provided to address the latency in the primary elements, which would result in undesired operation of the filter. Several configurations of suitable filters are discussed, including multi-rate filters and filters with reduced power requirements.

摘要翻译： 一种使用FIR和/或IIR元件的滤波器处理信号的系统和方法。 所需的控制器功能被分解成主FIR和/或IIR元件，并且提供补偿滤波器以解决主要元件中的延迟，这将导致滤波器的不期望的操作。 讨论了适当滤波器的几种配置，包括具有降低的功率要求的多速率滤波器和滤波器。

公开(公告)号：US09337805B2

公开(公告)日：2016-05-10

申请号：US13633092

申请日：2012-10-01

申请人： Creative Technology Ltd

发明人： David Philip Rossum

IPC分类号： H04B15/00 ,  H03H17/02 ,  H03H17/04

CPC分类号： H03H17/0288 ,  H03H17/0233 ,  H03H17/045 ,  H03H2017/0247 ,  H03H2017/0472

摘要： A new and more efficient filtering system (e.g., digital microphone decimation filter architecture system) is described. A key to this architecture is the use of two parallel filter paths. Each path operates at the output sample rate, and comprises a shorter FIR filter followed by a series of allpass stages (e.g., implementing IIR filters). The FIR filter is designed to remove all but the last octave of out-of-band noise. The allpass stages are designed such that when the two paths are summed together, the out-of-band noise for the final octave cancels out, leaving only the desired sign.

摘要翻译： 描述了一种新的和更有效的过滤系统（例如，数字麦克风抽取滤波器架构系统）。 该架构的关键是使用两个并行的过滤器路径。 每个路径以输出采样率运行，并且包括较短的FIR滤波器，随后是一系列全通级（例如，实现IIR滤波器）。 FIR滤波器被设计为除去带外噪声的最后八度以外的全部。 所有通道级被设计成使得当两个路径被相加在一起时，最终八度的带外噪声消除，仅留下期望的符号。

公开(公告)号：US20110022650A1

公开(公告)日：2011-01-27

申请号：US12812699

申请日：2009-01-08

申请人： Egbert Spiegel ,  Andreas Kribus

发明人： Egbert Spiegel ,  Andreas Kribus

IPC分类号： G06F17/10

CPC分类号： G01S15/104 ,  G01S15/931 ,  G01S2013/9314 ,  H03H17/0288 ,  H03H17/04

摘要： A digital optimal filter having an especially sinusoidal pulse response uses a filter structure with a recursive and a transversal portion. The transversal portion comprises filter coefficients for the representation of scan results of half a period of the sinusoidal pulse response signal. The recursive filter structure is used to change the sign after generation of the scan results for half a period and to mark the start and the end of the pulse response. A plurality of periods can lie in between the start and the end of the pulse response, this is why the digital optimal filter can be used to extract especially sinusoidal burst signals from an original signal, namely in digital technology, which is advantageous for the implementation of IC's.

摘要翻译： 具有特别正弦波脉冲响应的数字最优滤波器使用具有递归和横向部分的滤波器结构。 横向部分包括用于表示正弦脉冲响应信号的半个周期的扫描结果的滤波器系数。 递归滤波器结构用于在扫描结果生成半个周期之后改变符号，并标记脉冲响应的开始和结束。 多个周期可以位于脉冲响应的开始和结束之间，这就是为什么可以使用数字最优滤波器来从原始信号（即在数字技术中）提取特别是正弦的脉冲串信号，这对于实现是有利的 的IC。

公开(公告)号：US07139146B2

公开(公告)日：2006-11-21

申请号：US10484427

申请日：2003-05-22

申请人： Tomoyuki Hiura ,  Hiroyuki Ino

发明人： Tomoyuki Hiura ,  Hiroyuki Ino

IPC分类号： G11B5/09

CPC分类号： H03H17/0288 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/10055 ,  G11B20/10083 ,  G11B20/10101

摘要： A replay signal, obtained on reproducing a recording medium, on which has been recorded a digital signal, is supplied to an input terminal (1), and quantized by an A/D converter (8). The so quantized signal is processed by an integrator (20), formed by a first order IIR filter, so as to be adjusted in gain by an amplifier (21). The quantized replay signal is also processed by a differentiator formed by a combination of a first order FIR filter (22) and a first order IIR filter (23) so as to be then adjusted in gain by an amplifier (24). The resulting signal is then supplied to an adder (25) where it is subtracted from an output signal of the amplifier (21). In this manner, the differentiation/integration equalizer, formed by an analog circuit, is constructed by a digital circuit of a simplified configuration without raising the number of orders of the filters. The replay signal is processed by differentiation/integration such as to satisfy the equalization standard.

摘要翻译： 在再现已经记录了数字信号的记录介质上获得的重放信号被提供给输入端（1），由A / D转换器（8）进行量化。 这样量化的信号由由第一级IIR滤波器形成的积分器（20）处理，以便由放大器（21）调节增益。 量化的重放信号也由由一阶FIR滤波器（22）和一阶IIR滤波器（23）的组合形成的微分器处理，以便然后由放大器（24）调节增益。 然后将所得到的信号提供给加法器（25），在该加法器中从放大器（21）的输出信号中减去该加法器。 以这种方式，由模拟电路形成的微分/积分均衡器由简化配置的数字电路构成，而不增加滤波器的次数。 重放信号通过差分/积分来处理，以满足均衡标准。

公开(公告)号：US20060031275A1

公开(公告)日：2006-02-09

申请号：US11247302

申请日：2005-10-11

申请人： Richard Cannon

发明人： Richard Cannon

IPC分类号： G06F17/10

CPC分类号： H03H17/0288 ,  H03H17/0664 ,  H03H17/0671

摘要： A digital IF processing block including a decimation filter having FIR decimation stages provides improved performance over a Hogenauer decimating filter. The filter comprises multiple integrator stages followed by multiple FIR decimating stages. The zeros of the filter are tunable by adjusting the integer coefficients of the FIR stages providing tunability of the cut-off response, as opposed to the fixed sinc response of the Hogenauer filter. As a result, the number of required stages for a particular steepness is reduced, dramatically reducing the amount of digital circuitry required to implement a particular filter design. The improved filter is especially suitable for use in digital IF stages in receivers, and for code-based applications where selectable decimation rate is desired and a fast multiply is not available.

摘要翻译： 包括具有FIR抽取级的抽取滤波器的数字IF处理块提供了比Hogenau抽取滤波器更好的性能。 滤波器包括多个积分器级，随后是多个FIR抽取级。 通过调整FIR阶段的整数系数可以调节滤波器的零点，提供截止响应的可调性，而不是Hogenauer滤波器的固定sinc响应。 因此，特定陡度的所需级数减少，从而显着减少了实现特定滤波器设计所需的数字电路的数量。 改进的滤波器特别适用于接收机中的数字IF级，以及用于需要可选择抽取速率并且快速乘法不可用的基于代码的应用。

公开(公告)号：US20050283509A1

公开(公告)日：2005-12-22

申请号：US10871509

申请日：2004-06-18

申请人： Michael Hennedy ,  Vladimir Friedman ,  Artemas Speziale ,  Mohammad Sherkat

发明人： Michael Hennedy ,  Vladimir Friedman ,  Artemas Speziale ,  Mohammad Sherkat

IPC分类号： G06F15/16 ,  H03H17/02

CPC分类号： H03H17/0294 ,  H03H17/0288

摘要： A micro-programmable filter (MFE) engine includes multiple programmable filter elements and a microcode controller. The filter elements can be configured, controlled, and combined in different ways to implement different types of filters. The MFE preferably supports multiple-execution instructions that allow a single instruction to perform multiple moves into accumulators for efficient data movement inside MFE.

摘要翻译： 微型可编程滤波器（MFE）引擎包括多个可编程滤波器元件和微码控制器。 过滤器元件可以以不同的方式进行配置，控制和组合，以实现不同类型的过滤器。 MFE优选地支持多执行指令，其允许单个指令执行多次移动到累加器中以在MFE内有效地进行数据移动。

公开(公告)号：US20050168361A1

公开(公告)日：2005-08-04

申请号：US11017021

申请日：2004-12-20

申请人： Seyed Azizi

发明人： Seyed Azizi

IPC分类号： H03H17/02 ,  H03H17/04 ,  H03M7/00

CPC分类号： H03H17/0416 ,  H03H17/0288

摘要： A sample rate converter for converting a digital input signal having a first sample rate into a digital output signal having a second sample rate, wherein the second sample rate is different from the first sample rate. The sample rate converter includes a digital interpolation filter receiving the input signal and comprising a digital zero-phase filter, and a digital polynom interpolator connected to the interpolation filter and providing the output signal.

摘要翻译： 一种用于将具有第一采样率的数字输入信号转换为具有第二采样率的数字输出信号的采样率转换器，其中第二采样率不同于第一采样率。 采样率转换器包括接收输入信号并包括数字零相位滤波器的数字内插​​滤波器和连接到内插滤波器并提供输出信号的数字多项式插值器。

公开(公告)号：US20030235245A1

公开(公告)日：2003-12-25

申请号：US10321508

申请日：2002-12-18

发明人： Alper Tunga Erdogan ,  Bijit Halder ,  Tzu-Hsien Sang

IPC分类号： H03K005/159 ,  H03H007/30

CPC分类号： H04L1/0057 ,  H03H17/0288 ,  H03M13/235 ,  H03M13/253 ,  H03M13/256 ,  H03M13/2936 ,  H04L1/0041 ,  H04L1/0042 ,  H04L1/0045 ,  H04L1/0047 ,  H04L1/0059 ,  H04L1/006 ,  H04L25/03063 ,  H04L27/02 ,  H04L27/2608 ,  H04L27/3405 ,  H04L27/3433 ,  H04L2025/03414 ,  H04L2025/03503 ,  H04L2025/03509 ,  H04L2025/03611

摘要： According to an embodiment of present invention, an algorithm for computing static pre-equalizer coefficients, comprises the steps of determining a length of algorithm iterations; calculating a feedforward coefficient vector associated with a feedforward equalizer; calculating a pre-equalizer coefficient vector associated with a pre-equalizer filter; and performing the steps of calculating for the length of the algorithm iterations; wherein a mean square of an error between an output sequence and a transmitted digital input sequence is minimized.

摘要翻译： 根据本发明的实施例，一种用于计算静态预均衡器系数的算法，包括确定算法迭代长度的步骤; 计算与前馈均衡器相关联的前馈系数向量; 计算与预均衡器滤波器相关联的预均衡器系数向量; 以及执行所述算法迭代的长度的计算步骤; 其中输出序列和发送的数字输入序列之间的误差的均方最小。

公开(公告)号：US20020105447A1

公开(公告)日：2002-08-08

申请号：US10061700

申请日：2002-02-01

发明人： Markus Freidhof ,  Kurt Schmidt

IPC分类号： H03M007/00

CPC分类号： H03H17/0288 ,  H03H17/0671 ,  H03M7/00

摘要： A resampler converts a digital input sequence with an input sampling into a digital output signal sequence with an output sampling rate. An estimation device estimates the sampling rate ratio between the input sampling rate and the output sampling rate and the desired phase of the output signal sequence in an observation interval with a predetermined length of N samples of the output signal sequence, the observation intervals overlapping in the ratio 1:6. A control device compares the actual phase of the output signal sequence with the desired phase and, in a manner dependent on the estimated sampling rate ratio and the deviation of the actual phase from the desired phase, generates a control signal for in each case N/6 samples of the output signal sequence. An interpolator interpolates the input signal sequence for the purpose of generating the output signal sequence at sampling instants whose temporal position is predetermined by a control signal.

摘要翻译： 重采样器将具有输入采样的数字输入序列转换成具有输出采样率的数字输出信号序列。 估计装置在输出信号序列的N个样本的预定长度的观察间隔中估计输入采样率和输出采样率之间的输出采样率和期望相位之间的采样率比， 比例1：6。 控制装置将输出信号序列的实际相位与期望的相位进行比较，并且以取决于估计的采样率比率和实际相位与期望相位的偏差的方式进行比较，生成控制信号，在每种情况下，N / 6个样本的输出信号序列。 内插器内插输入信号序列，以便在其时间位置由控制信号预定的采样时刻产生输出信号序列。

公开(公告)号：US20020051502A1

公开(公告)日：2002-05-02

申请号：US10024852

申请日：2001-12-19

发明人： Lennart Mathe

IPC分类号： H04L027/22 ,  H04L027/14 ,  H04L027/06

CPC分类号： H03H17/0294 ,  H03H17/0288

摘要： A low power programmable digital filter adapted for use with a telecommunications system transceiver. The digital filter includes a first finite impulse response filter section for receiving an input signal and having a first transfer function. An infinite impulse response filter section is connected to the first finite impulse response filter section and has a second transfer function. A second finite impulse response filter section is connected to the infinite impulse response filter section and outputs a filtered output signal in response the receipt of the input signal by the programmable digital filter. The second finite impulse response filter section has a third transfer function. A programmable coefficient is included in the first, second, and/or the third transfer function.

摘要翻译： 适用于电信系统收发器的低功率可编程数字滤波器。 数字滤波器包括用于接收输入信号并具有第一传递函数的第一有限脉冲响应滤波器部分。 无限脉冲响应滤波器部分连接到第一有限脉冲响应滤波器部分并且具有第二传递函数。 第二有限脉冲响应滤波器部分连接到无限脉冲响应滤波器部分，并且响应于可编程数字滤波器接收到输入信号而输出滤波后的输出信号。 第二有限脉冲响应滤波器部分具有第三传递函数。 可编程系数包括在第一，第二和/或第三传递函数中。