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    Power supply noise cancelling circuit and power supply noise cancelling method
    1.
    发明授权
    Power supply noise cancelling circuit and power supply noise cancelling method 有权
    电源噪声消除电路和电源噪声消除方法

    公开(公告)号：US09240797B2

    公开(公告)日：2016-01-19

    申请号：US14657728

    申请日：2015-03-13

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Kei Shiraishi ,  Masanori Furuta ,  Junya Matsuno ,  Tetsuro Itakura

    IPC分类号： H03M1/66 ,  H03M1/08 ,  H03M1/00

    CPC分类号： H03M1/0836 ,  H03M1/001 ,  H03M1/08 ,  H03M1/0845 ,  H03M1/66 ,  H03M1/665 ,  H03M1/742

    摘要： According to an embodiment, a power supply noise cancelling circuit includes a generator, a first multiplier, a subtractor and a digital-to-analog converter. The generator generates a sine wave signal. The first multiplier multiplies a digital input signal by a digital signal based on the sine wave signal to generate a first digital product signal. The subtractor subtracts a digital signal based on the first digital product signal from the digital input signal to generate a digital difference signal. The digital-to-analog converter performs a digital-to-analog conversion on the digital difference signal to obtain an analog output signal.

    摘要翻译： 根据实施例，电源噪声消除电路包括发生器，第一乘法器，减法器和数模转换器。 发生器产生正弦波信号。 第一乘法器基于正弦波信号将数字输入信号乘以数字信号以产生第一数字乘积信号。 减法器基于来自数字输入信号的第一数字乘积信号减去数字信号，以产生数字差分信号。 数模转换器对数字差分信号执行数模转换以获得模拟输出信号。

    Modular Units for Synchro-to-Digital Conversion and Digital-to-Synchro Conversion
    2.
    发明申请
    Modular Units for Synchro-to-Digital Conversion and Digital-to-Synchro Conversion 失效
    用于同步到数字转换和数字到同步转换的模块化单元

    公开(公告)号：US20110037627A1

    公开(公告)日：2011-02-17

    申请号：US12916020

    申请日：2010-10-29

    申请人： Charles J. Hermann

    发明人： Charles J. Hermann

    IPC分类号： H03M1/48

    CPC分类号： H03M1/645 ,  H03M1/665

    摘要： The inventive data conversion device is typically embodied as a modular unit including a PCBA and a frame that houses it. The PCBA includes a PCB and electronic components mounted thereon including a computer and one or more conventional conversion devices, viz., at least one conventional synchro-to-digital converter and/or at least one conventional digital-to-synchro converter. According to typical inventive synchro-to-digital conversion, analog synchro data (received from a synchro) is converted by the synchro-to-digital converter(s) to lower-level-format parallel-binary-angle digital synchro data, which in turn is converted by the computer to higher-level-format digital synchro data. According to typical inventive digital-to-synchro conversion, higher-level-format digital synchro data (received from a modern-day digital device/system/network) is converted by the computer to lower-level-format parallel-binary-angle digital synchro data, which in turn is converted by the digital-to-synchro converter(s) to analog synchro data.

    摘要翻译： 本发明的数据转换装置通常被实施为包括PCBA和容纳它的框架的模块化单元。 PCBA包括安装在其上的PCB和电子部件，其包括计算机和一个或多个常规转换装置，即至少一个常规的同步数字转换器和/或至少一个常规的数字至同步转换器。 根据典型的本发明的同步到数字转换，模拟同步数据（从同步接收）由同步到数字转换器转换成较低级格式的并行二角角数字同步数据， 电脑转换成高级格式的数字同步数据。 根据典型的创新的数字到同步转换，较高级格式的数字同步数据（从现代数字设备/系统/网络接收）由计算机转换为较低级格式的并行二进制角度数字 同步数据，其又由数字到同步转换器转换成模拟同步数据。

    Correction circuit for a digital to synchro/resolver converter
    3.
    发明授权
    Correction circuit for a digital to synchro/resolver converter 失效
    数字同步/解算器转换器的校正电路

    公开(公告)号：US4157538A

    公开(公告)日：1979-06-05

    申请号：US853341

    申请日：1977-11-21

    申请人： David J. Simon ,  Edward C. Costello

    发明人： David J. Simon ,  Edward C. Costello

    IPC分类号： H03M1/00 ,  H03K13/02

    CPC分类号： H03M1/0604 ,  H03M1/665

    摘要： In a digital to synchro/resolver converter which has an intrinsic transformation ratio variation with respect to input angle greater than desired in a given application, the intrinsic variation is corrected by applying a correction to the reference voltage used in carrying out the digital to synchro conversion.

    摘要翻译： 在相对于给定应用中所需的输入角度具有固有变换比变化的数字到同步/分解变换器中，通过对用于执行数字到同步转换的参考电压应用校正来校正本征变化 。

    Multi-bit function generator
    4.
    发明授权
    Multi-bit function generator 失效
    多位函数发生器

    公开(公告)号：US4119959A

    公开(公告)日：1978-10-10

    申请号：US723111

    申请日：1976-09-14

    申请人： Seymour Lanton

    发明人： Seymour Lanton

    IPC分类号： G06G7/22 ,  G06G7/26 ,  H03M1/00 ,  H03K13/00

    CPC分类号： H03M1/645 ,  G06G7/26 ,  H03M1/665

    摘要： A function generator for use in a synchro to digital (S to D) converter in which successive approximations of the digital output are made by switching between two chains of cascade connected operational amplifiers so that, as one chain is incremented to decrease the error signal appearing at the output of the chain, the other chain is coupled to control the error reduction operation until the aforementioned switching is completed, at which time the chains reverse roles.

    摘要翻译： 一种用于同步到数字（S至D）转换器的函数发生器，其中通过在级联连接的运算放大器的两个链之间切换来进行数字输出的逐次逼近，使得当一个链增加以减少出现的误差信号 在链的输出处，另一条链被连接以控制误差减少操作，直到上述的切换完成为止，此时链反向。