公开(公告)号：US20070124656A1

公开(公告)日：2007-05-31

申请号：US11501335

申请日：2006-08-09

Applicant: Eran Pisek ,  Yan Wang ,  Jasmin Oz

Inventor： Eran Pisek ,  Yan Wang ,  Jasmin Oz

IPC: H03M13/03

CPC classification number: H03M13/3983 ,  H03M13/2957 ,  H03M13/2969 ,  H03M13/3911 ,  H03M13/6508 ,  H03M13/6513 ,  H03M13/6561

Abstract: A reconfigurable maximum a-posteriori probability (MAP) calculation circuit that reuses the arithmetic logic unit (ALU) hardware to calculate forward state metrics (alpha values), backward state metrics (beta values), and extrinsic information (lambda values) for the trellis associated with the MAP algorithm. The alpha, beta and lambda calculations may be performed by the same ALU hardware for both binary code (i.e., WCDMA mode) and duo-binary code (i.e, WiBro mode).

Abstract translation: 可重构的最大后验概率（MAP）计算电路，其重用算术逻辑单元（ALU）硬件来计算网格的前向状态度量（α值），向后状态度量（β值）和外在信息（λ值） 与MAP算法相关联。 对于二进制码（即WCDMA模式）和二进制二进制码（即WiBro模式），alpha，beta和lambda计算可由相同的ALU硬件来执行。

公开(公告)号：US20060093046A1

公开(公告)日：2006-05-04

申请号：US10530323

申请日：2003-10-02

Applicant: Makoto Nakamura

Inventor： Makoto Nakamura

IPC: H04B14/04

CPC classification number: H03M13/3983 ,  H03M13/235 ,  H03M13/256 ,  H04L1/0054 ,  H04L1/0059 ,  H04L27/2057 ,  H04L27/2332

Abstract: A digital communication device includes: a modulator having encoding means for converting two-dimensional digital information signal into a three-dimensional signal and phase modulation means for modifying the carrier phase in according to the three-dimensional signal; and a demodulator having phase demodulation means for detecting information on the three-dimensional signal from the received phase-modulated wave and demodulation means for deciding the two-dimensional digital information from the information on the three-dimensional signal. The digital communication device has a bit error ratio and an occupied radio band width equivalent to a digital communication device using the conventional QPSK or π/4 shift QPSK and the error correction method and greatly improves the amplitude fluctuation. Moreover, the digital communication device can transmit a signal with a narrower occupied frequency band width while maintaining the same constant envelope characteristic as the GMSK using the conventional error correction code.

Abstract translation: 数字通信装置包括：具有用于将二维数字信息信号转换为三维信号的编码装置的调制器和用于根据三维信号修改载波相位的相位调制装置; 以及解调器，具有用于从接收到的相位调制波检测关于三维信号的信息的相位解调装置和用于根据关于三维信号的信息来确定二维数字信息的解调装置。 数字通信设备具有与使用传统的QPSK或者pi / 4移位QPSK的数字通信设备相当的比特误差率和占用的无线电带宽以及纠错方法，并且极大地改善了振幅波动。 此外，数字通信设备可以使用传统的纠错码在保持与GMSK保持相同的恒定包络特性的同时发送具有较窄占用频带宽度的信号。

公开(公告)号：US20100299579A1

公开(公告)日：2010-11-25

申请号：US12774092

申请日：2010-05-05

Applicant: Peter Lablans

Inventor： Peter Lablans

IPC: H03M13/07 ,  G06F11/10

CPC classification number: H03M13/235 ,  H03M13/3983

Abstract: Convolutional coders having an n-state with n≧2 Linear Feedback Shift Registers (LFSR) in Galois configuration with k shift register elements with k>1 are provided. Corresponding decoders are also provided. A convolutional coder generates a sequence of coded n-state symbols. A content of a starting position of an LFSR in a decoder is determined when sufficient error free coded symbols are available. Up to k symbols in error are corrected. A systematic convolutional coder and decoder are also provided.

Abstract translation: 提供具有n≥2的具有n≥2的线性反馈移位寄存器（LFSR）在具有k> 1的k个移位寄存器元件的Galois配置中的卷积编码器。 还提供了相应的解码器。 卷积编码器生成编码的n态符号序列。 当有足够的无差错编码符号可用时，确定解码器中LFSR的起始位置的内容。 纠正错误的k个符号。 还提供了系统卷积编码器和解码器。

公开(公告)号：US20080123781A1

公开(公告)日：2008-05-29

申请号：US11605525

申请日：2006-11-29

Applicant: Eran Pisek ,  Thomas M. Henige

Inventor： Eran Pisek ,  Thomas M. Henige

IPC: H04L27/06 ,  G06F11/07

CPC classification number: H04L1/0055 ,  H03M13/2969 ,  H03M13/3905 ,  H03M13/3911 ,  H03M13/3972 ,  H03M13/3983 ,  H03M13/6569 ,  H04L1/005 ,  H04L1/0052 ,  H04L1/0057 ,  H04L1/0066

Abstract: A maximum a posteriori probability (MAP) block decoder for decoding a received data block of input samples. The MAP block decoder segments the received data block into at least a first segment and a second segment and calculates and stores alpha values during forward processing of the first segment. The MAP block decoder uses a first selected alpha value calculated during forward processing of the first segment as initial state information during forward processing of the second segment. The first and second segments may overlap each other, such that the last M samples of the first segment are the same as the first M samples of the second segment.

Abstract translation: 用于对输入样本的接收数据块进行解码的最大后验概率（MAP）块解码器。 MAP块解码器将接收的数据块分段成至少第一段和第二段，并且在第一段的正向处理期间计算并存储α值。 MAP块解码器使用在第一段的正向处理期间计算的第一选择的α值作为第二段的正向处理期间的初始状态信息。 第一和第二段可以彼此重叠，使得第一段的最后M个样本与第二段的前M个样本相同。

公开(公告)号：US09385757B1

公开(公告)日：2016-07-05

申请号：US14031637

申请日：2013-09-19

Applicant: Marvell International Ltd.

Inventor： Nitin Nangare

IPC: H03M13/41 ,  H03M13/25 ,  H03M13/53 ,  H04L1/00

CPC classification number: H03M13/256 ,  H03M13/3983 ,  H03M13/41 ,  H03M13/4146 ,  H04L1/006

Abstract: Systems and methods are provided for generating a likelihood value. A detector identifies a winning path through a trellis and a plurality of losing paths through the trellis and computes path metric differences within the trellis based on the winning path and at least some of the plurality of losing paths. The detector calculates a pair of error metrics based on the path metric differences and determines the likelihood value based on a difference between the pair of error metrics.

Abstract translation: 提供了用于生成似然值的系统和方法。 检测器通过网格和通过网格的多个丢失路径识别获胜路径，并且基于获胜路径和多个丢失路径中的至少一些来计算网格内的路径度量差异。 检测器基于路径度量差计算一对误差量度，并且基于该对误差度量之间的差异来确定似然值。

公开(公告)号：US07895497B2

公开(公告)日：2011-02-22

申请号：US11605525

申请日：2006-11-29

Applicant: Eran Pisek ,  Thomas M. Henige

Inventor： Eran Pisek ,  Thomas M. Henige

IPC: H03M13/00

CPC classification number: H04L1/0055 ,  H03M13/2969 ,  H03M13/3905 ,  H03M13/3911 ,  H03M13/3972 ,  H03M13/3983 ,  H03M13/6569 ,  H04L1/005 ,  H04L1/0052 ,  H04L1/0057 ,  H04L1/0066

Abstract: A maximum a posteriori probability (MAP) block decoder for decoding a received data block of input samples. The MAP block decoder segments the received data block into at least a first segment and a second segment and calculates and stores alpha values during forward processing of the first segment. The MAP block decoder uses a first selected alpha value calculated during forward processing of the first segment as initial state information during forward processing of the second segment. The first and second segments may overlap each other, such that the last M samples of the first segment are the same as the first M samples of the second segment.

Abstract translation: 用于对输入样本的接收数据块进行解码的最大后验概率（MAP）块解码器。 MAP块解码器将接收的数据块分段成至少第一段和第二段，并且在第一段的正向处理期间计算并存储α值。 MAP块解码器使用在第一段的正向处理期间计算的第一选择的α值作为第二段的正向处理期间的初始状态信息。 第一和第二段可以彼此重叠，使得第一段的最后M个样本与第二段的前M个样本相同。

公开(公告)号：US07669105B2

公开(公告)日：2010-02-23

申请号：US11501335

申请日：2006-08-09

Applicant: Eran Pisek ,  Yan Wang ,  Jasmin Oz

Inventor： Eran Pisek ,  Yan Wang ,  Jasmin Oz

IPC: H03M13/00

CPC classification number: H03M13/3983 ,  H03M13/2957 ,  H03M13/2969 ,  H03M13/3911 ,  H03M13/6508 ,  H03M13/6513 ,  H03M13/6561

Abstract: A reconfigurable maximum a-posteriori probability (MAP) calculation circuit that reuses the arithmetic logic unit (ALU) hardware to calculate forward state metrics (alpha values), backward state metrics (beta values), and extrinsic information (lambda values) for the trellis associated with the MAP algorithm. The alpha, beta and lambda calculations may be performed by the same ALU hardware for both binary code (i.e., WCDMA mode) and duo-binary code (i.e, WiBro mode).

Abstract translation: 可重构的最大后验概率（MAP）计算电路，其重用算术逻辑单元（ALU）硬件来计算网格的前向状态度量（α值），向后状态度量（β值）和外在信息（λ值） 与MAP算法相关联。 对于二进制码（即WCDMA模式）和二进制二进制码（即WiBro模式），alpha，beta和lambda计算可由相同的ALU硬件来执行。

公开(公告)号：US08661324B2

公开(公告)日：2014-02-25

申请号：US13227538

申请日：2011-09-08

Applicant: Shaohua Yang ,  Weijun Tan ,  Zongwang Li ,  Fan Zhang ,  Yang Han ,  Chung-Li Wang ,  Wu Chang

Inventor： Shaohua Yang ,  Weijun Tan ,  Zongwang Li ,  Fan Zhang ,  Yang Han ,  Chung-Li Wang ,  Wu Chang

IPC: H03M13/00

CPC classification number: H03M13/1102 ,  G11B20/10379 ,  G11B27/36 ,  G11B2220/2516 ,  H03M13/1111 ,  H03M13/3983 ,  H03M13/45 ,  H03M13/6569

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detector circuit, a biasing circuit, and a data decoder circuit. The data detector circuit is operable to apply a data detection algorithm to a series of symbols to yield a detected output, and the detected output includes a series of soft decision data corresponding to non-binary symbols. The biasing circuit is operable apply a bias to each of the series of soft decision data to yield a series of biased soft decision data. The data decoder circuit is operable to apply a data decoding algorithm to the series of biased soft decision data corresponding to the non-binary symbols.

Abstract translation: 本发明的各种实施例提供了用于数据处理的系统和方法。 作为示例，公开了包括数据检测器电路，偏置电路和数据解码器电路的数据处理电路。 数据检测器电路可操作以将数据检测算法应用于一系列符号以产生检测到的输出，并且所检测的输出包括与非二进制符号对应的一系列软判决数据。 偏置电路可操作地将偏置应用于该系列软判决数据中的每一个，以产生一系列偏置的软判决数据。 数据解码器电路可操作以将数据解码算法应用于对应于非二进制符号的一系列偏置软判决数据。

公开(公告)号：US20130067297A1

公开(公告)日：2013-03-14

申请号：US13227538

申请日：2011-09-08

Applicant: Shaohua Yang ,  Weijun Tan ,  Zongwang Li ,  Fan Zhang ,  Yang Han ,  Chung-Li Wang ,  Wu Chang

Inventor： Shaohua Yang ,  Weijun Tan ,  Zongwang Li ,  Fan Zhang ,  Yang Han ,  Chung-Li Wang ,  Wu Chang

IPC: H03M13/45 ,  G06F11/10

CPC classification number: H03M13/1102 ,  G11B20/10379 ,  G11B27/36 ,  G11B2220/2516 ,  H03M13/1111 ,  H03M13/3983 ,  H03M13/45 ,  H03M13/6569

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detector circuit, a biasing circuit, and a data decoder circuit. The data detector circuit is operable to apply a data detection algorithm to a series of symbols to yield a detected output, and the detected output includes a series of soft decision data corresponding to non-binary symbols. The biasing circuit is operable apply a bias to each of the series of soft decision data to yield a series of biased soft decision data. The data decoder circuit is operable to apply a data decoding algorithm to the series of biased soft decision data corresponding to the non-binary symbols.

Abstract translation: 本发明的各种实施例提供了用于数据处理的系统和方法。 作为示例，公开了包括数据检测器电路，偏置电路和数据解码器电路的数据处理电路。 数据检测器电路可操作以将数据检测算法应用于一系列符号以产生检测到的输出，并且所检测的输出包括与非二进制符号对应的一系列软判决数据。 偏置电路可操作地将偏置应用于该系列软判决数据中的每一个，以产生一系列偏置的软判决数据。 数据解码器电路可操作以将数据解码算法应用于对应于非二进制符号的一系列偏置软判决数据。

公开(公告)号：US20050094749A1

公开(公告)日：2005-05-05

申请号：US10980074

申请日：2004-11-03

Applicant: Cheng-Ting Wu ,  Hung-Ming Chang

Inventor： Cheng-Ting Wu ,  Hung-Ming Chang

IPC: G06F12/00 ,  H03M13/41 ,  H04L27/06

CPC classification number: H03M13/6505 ,  H03M13/3983 ,  H03M13/41

Abstract: The present invention provides a non-binary Viterbi data processing system comprising a non-binary Viterbi processor, a path metric memory, and a memory access device. The non-binary Viterbi processor is used for obtaining the path metrics of a set of states according to a Viterbi decoding procedure. The path metric memory comprises memory units of the same amount as the states. The memory units are depicted by combinations of symbols for storing the corresponding path metrics of the set of states. The memory access device is used for reading out the path metrics from the path metric memory for calculation by the non-binary Viterbi processor, and for writing the updated path metrics back to the path metric memory. Therefore, merely the same amounts of the memory units as the states in the path metric memory are required for update of the set of path metrics.

Abstract translation: 本发明提供一种非二进制维特比数据处理系统，其包括非二进制维特比处理器，路径度量存储器和存储器访问装置。 非二进制维特比处理器用于根据维特比解码过程获得一组状态的路径度量。 路径度量存储器包括与状态相同量的存储器单元。 存储器单元由用于存储该组状态的相应路径度量的符号的组合来描绘。 存储器访问装置用于从路径度量存储器读出用于由非二进制维特比处理器计算的路径度量，并用于将更新的路径度量写回到路径度量存储器。 因此，仅需要与路径度量存储器中的状态相同量的存储器单元来更新路径度量集合。