公开(公告)号：US6064227A

公开(公告)日：2000-05-16

申请号：US059248

申请日：1998-04-14

申请人： Toshiaki Saito

发明人： Toshiaki Saito

IPC分类号： H03K19/0185 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/094 ,  H03K19/00 ,  H03K19/20 ,  G05K3/02

CPC分类号： H03K19/00315

摘要： In an output buffer circuit, a logic circuit generates first and second data signals each having a voltage level between a low voltage and a first high voltage. A level shift circuit receives the first data signal and generates a third data signal having a voltage between a first intermediate voltage and a second high voltage higher than the first high voltage. An output circuit includes first and second P-channel MOS transistors and first and second N-channel MOS transistors powered by the low voltage and the second high voltage, a gate of the first P-channel MOS transistor receives the third data signal, a gate of the second P-channel MOS transistor receives a second intermediate voltage between the low voltage and the second high voltage, a gate of the first N-channel MOS transistor receives the data signal, and a gate of the second N-channel MOS transistor receives a third intermediate voltage.

摘要翻译： 在输出缓冲器电路中，逻辑电路产生每个具有低电压和第一高电压之间的电压电平的第一和第二数据信号。 电平移位电路接收第一数据信号并产生具有高于第一高电压的第一中间电压和第二高电压之间的电压的第三数据信号。 输出电路包括第一和第二P沟道MOS晶体管以及由低电压和第二高电压供电的第一和第二N沟道MOS晶体管，第一P沟道MOS晶体管的栅极接收第三数据信号，栅极 所述第二P沟道MOS晶体管接收所述低电压和所述第二高电压之间的第二中间电压，所述第一N沟道MOS晶体管的栅极接收所述数据信号，并且所述第二N沟道MOS晶体管的栅极接收 第三中间电压。

公开(公告)号：US06938334B2

公开(公告)日：2005-09-06

申请号：US10698214

申请日：2003-10-31

申请人： Lianzhong Yu

发明人： Lianzhong Yu

IPC分类号： B81C3/00 ,  G01P15/08 ,  G01P15/097 ,  H05K3/36 ,  G05K3/02

CPC分类号： B81C3/002 ,  B81B2201/0235 ,  B81C2201/019 ,  B81C2203/051 ,  G01P15/0802 ,  G01P15/097 ,  Y10T29/49126 ,  Y10T29/49155

摘要： A method for fabrication of microelectromechanical systems (MEMS) integrated micro devices and acceleration sensor devices formed according to the method, the method being micromachining an array of first three-dimensional micromechanical device features in a first silicon wafer; micromachining an array of second three-dimensional micromechanical device features in a second silicon wafer, wherein the second three-dimensional micromechanical device features are configured to cooperate with the first three-dimensional micromechanical device features when joined therewith; mutually aligning the first and second arrays of device features by aligning the first and second wafers; permanently joining the first and second arrays of device features into an array of integrated micro devices as a function of permanently joining the first and second wafers into a single composite wafer; and subsequently separating the array of integral devices into individual devices each having a set of the first and second device features.

摘要翻译： 一种用于制造根据该方法形成的微机电系统（MEMS）集成微型装置和加速度传感器装置的方法，所述方法是微加工第一硅晶片中的第一三维微机械装置特征的阵列; 在第二硅晶片中微加工第二三维微机械器件特征的阵列，其中所述第二三维微机械器件特征被配置为当与所述第二三维微机械器件特征连接时与所述第一三维微机械器件特征协作; 通过对准第一和第二晶片来相互对准器件特征的第一和第二阵列; 将第一和第二器件特征阵列永久地连接到集成微器件的阵列中，作为将第一和第二晶片永久地连接到单个复合晶片中的功能; 并且随后将所述整体设备阵列分离成各自具有所述第一和第二设备特征的集合的单独设备。