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    Nonvolatile semiconductor memory device capable of concurrently and reliably writing/erasing and reading memory cores
    1.
    发明授权
    Nonvolatile semiconductor memory device capable of concurrently and reliably writing/erasing and reading memory cores 有权
    能够同时且可靠地写入/擦除和读取存储器核的非易失性半导体存储器件

    公开(公告)号：US06717852B2

    公开(公告)日：2004-04-06

    申请号：US10267693

    申请日：2002-10-10

    申请人： Yasuhiko Honda ,  Hideo Kato ,  Masao Kuriyama ,  Hidetoshi Saito ,  Tokumasa Hara

    发明人： Yasuhiko Honda ,  Hideo Kato ,  Masao Kuriyama ,  Hidetoshi Saito ,  Tokumasa Hara

    IPC分类号： G11C1632

    CPC分类号： G11C16/08 ,  G11C7/1042 ,  G11C16/10 ,  G11C16/26 ,  G11C2216/22

    摘要： A semiconductor memory device, which allows concurrent execution of a write/erase operation and a read operation, is provided for each core with a core busy output circuit which has a function of, at the start, end, suspending or resuming of a write/erase operation, setting the sequence in which a command to write into/erase or read from a core, a core select signal indicating whether or not the core has been selected, and a busy signal indicating that the core is in the write/erase mode are set or reset so that multiple selection of a core in a write/erase operation and a core in a read operation does not occur.

    摘要翻译： 为每个核心提供一个允许并行执行写入/擦除操作和读取操作的半导体存储器件，其具有核心忙输出电路，其具有在开始和结束时挂起或恢复写/ 擦除操作，设置写入/擦除或从内核读取的命令的顺序，指示核心是否被选择的核心选择信号以及指示核心处于写/擦除模式的忙信号 被设置或复位，使得在写入/擦除操作中的核心和读取操作中的核心不会发生多次选择。

    Nonvolatile semiconductor memory device capable of controlling mutual timing of write voltage pulse and transfer voltage pulse
    2.
    发明授权
    Nonvolatile semiconductor memory device capable of controlling mutual timing of write voltage pulse and transfer voltage pulse 失效
    非易失性半导体存储器件能够控制写入电压脉冲和转换电压脉冲的相互定时

    公开(公告)号：US06252798B1

    公开(公告)日：2001-06-26

    申请号：US09104163

    申请日：1998-06-25

    申请人： Shinji Satoh ,  Riichiro Shirota ,  Toru Tanzawa

    发明人： Shinji Satoh ,  Riichiro Shirota ,  Toru Tanzawa

    IPC分类号： G11C1632

    CPC分类号： G11C16/32 ,  G11C16/0483 ,  G11C16/08

    摘要： A nonvolatile semiconductor memory device comprises a memory cell array having plural electrically erasable memory cells including a gate, a source, a drain, and an electric charge accumulation layer each disposed in a matrix form. A data writing section writes data into memory cells in this memory cell array. A data reading section reads out data in memory cells of the memory cell array. A data erasing section erases data in memory cells of the memory cell array. A control section controls, when applying a first signal to the gate in a specified memory inhibited of writing and applying a second signal to a node capacitively coupled to at least one of source and drain, in writing data into the memory cells, so that the second signal may fall later than the first signal.

    摘要翻译： 非易失性半导体存储器件包括具有多个电可擦除存储单元的存储单元阵列，每个电可擦除存储单元包括以矩阵形式设置的栅极，源极，漏极和电荷累积层。 数据写入部分将数据写入该存储单元阵列中的存储单元。 数据读取部读出存储单元阵列的存储单元中的数据。 数据擦除部分擦除存储单元阵列的存储单元中的数据。 控制部分在将指定的存储器中的门施加禁止写入的第一信号并且将第二信号施加到电容耦合到源极和漏极中的至少一个的节点时控制将数据写入存储器单元中，从而使得 第二信号可能晚于第一信号。