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    Nonvolatile semiconductor memory device capable of controlling mutual timing of write voltage pulse and transfer voltage pulse
    1.
    发明授权
    Nonvolatile semiconductor memory device capable of controlling mutual timing of write voltage pulse and transfer voltage pulse 失效
    非易失性半导体存储器件能够控制写入电压脉冲和转换电压脉冲的相互定时

    公开(公告)号：US06252798B1

    公开(公告)日：2001-06-26

    申请号：US09104163

    申请日：1998-06-25

    申请人： Shinji Satoh ,  Riichiro Shirota ,  Toru Tanzawa

    发明人： Shinji Satoh ,  Riichiro Shirota ,  Toru Tanzawa

    IPC分类号： G11C1632

    CPC分类号： G11C16/32 ,  G11C16/0483 ,  G11C16/08

    摘要： A nonvolatile semiconductor memory device comprises a memory cell array having plural electrically erasable memory cells including a gate, a source, a drain, and an electric charge accumulation layer each disposed in a matrix form. A data writing section writes data into memory cells in this memory cell array. A data reading section reads out data in memory cells of the memory cell array. A data erasing section erases data in memory cells of the memory cell array. A control section controls, when applying a first signal to the gate in a specified memory inhibited of writing and applying a second signal to a node capacitively coupled to at least one of source and drain, in writing data into the memory cells, so that the second signal may fall later than the first signal.

    摘要翻译： 非易失性半导体存储器件包括具有多个电可擦除存储单元的存储单元阵列，每个电可擦除存储单元包括以矩阵形式设置的栅极，源极，漏极和电荷累积层。 数据写入部分将数据写入该存储单元阵列中的存储单元。 数据读取部读出存储单元阵列的存储单元中的数据。 数据擦除部分擦除存储单元阵列的存储单元中的数据。 控制部分在将指定的存储器中的门施加禁止写入的第一信号并且将第二信号施加到电容耦合到源极和漏极中的至少一个的节点时控制将数据写入存储器单元中，从而使得 第二信号可能晚于第一信号。

    Error correction/detection circuit and semiconductor memory device using the same
    3.
    发明授权
    Error correction/detection circuit and semiconductor memory device using the same 失效
    误差校正/检测电路及使用其的半导体存储器件

    公开(公告)号：US5933436A

    公开(公告)日：1999-08-03

    申请号：US611818

    申请日：1996-03-06

    申请人： Toru Tanzawa ,  Tomoharu Tanaka ,  Riichiro Shirota ,  Kazunori Ohuchi

    发明人： Toru Tanzawa ,  Tomoharu Tanaka ,  Riichiro Shirota ,  Kazunori Ohuchi

    IPC分类号： G06F12/16 ,  G06F11/10 ,  H03M13/15 ,  G11C29/00

    CPC分类号： G06F11/1008 ,  H03M13/151

    摘要： An error correction/detection circuit including a syndrome generating circuit for generating a syndrome from information data and check data input in a first cycle; and an error position/size calculating circuit for calculating a position and a size of an error from said syndrome; and an error correction circuit for correcting an error for at least information data input in a second cycle on a basis of the position and the size of the error obtained in said error position/size calculating circuit and for outputting at least error-corrected information data.

    摘要翻译： 一种纠错/检测电路，包括：从第一周期输入的信息数据和检查数据产生校正子的校正子产生电路; 以及误差位置/尺寸计算电路，用于计算所述综合征的误差的位置和尺寸; 以及误差校正电路，用于根据在所述误差位置/尺寸计算电路中获得的误差的位置和尺寸，校正至少在第二周期中输入的信息数据的误差，并且至少输出错误校正的信息数据 。