公开(公告)号：US5714803A

公开(公告)日：1998-02-03

申请号：US508919

申请日：1995-07-28

申请人： Daniel G. Queyssac

发明人： Daniel G. Queyssac

IPC分类号： H01L23/32 ,  H01L23/48 ,  H01L23/498 ,  H05K3/32 ,  H05K7/10 ,  H01C23/48 ,  H01C23/52 ,  H01C29/40

CPC分类号： H05K7/1061 ,  H01L23/32 ,  H01L23/49816 ,  H01L24/72 ,  H05K3/325 ,  H01L2224/48091 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14

摘要： An integrated circuit package has leadless solderballs attached to the substrate with a conductive thermoplastic adhesive. The leadless solderballs are preferably made with a copper-nickel-gold alloy. The conductive thermoplastic is preferably of the silver fill type. The integrated circuit package is placed in a frame and held to the printed circuit board with a clamp or with a screw.

摘要翻译： 集成电路封装具有用导电热塑性粘合剂附着到基板上的无引线焊球。 无引线焊球优选由铜 - 镍 - 金合金制成。 导电性热塑性材料优选为银填充型。 集成电路封装放置在框架中，并用夹具或螺丝固定在印刷电路板上。

公开(公告)号：US5710460A

公开(公告)日：1998-01-20

申请号：US426303

申请日：1995-04-21

申请人： Robert Kenneth Leidy ,  Jeffrey Scott Miller ,  Jon A. Patrick ,  Rosemary Ann Previti-Kelly

发明人： Robert Kenneth Leidy ,  Jeffrey Scott Miller ,  Jon A. Patrick ,  Rosemary Ann Previti-Kelly

IPC分类号： H01L21/3205 ,  H01L21/304 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48 ,  H01L23/52 ,  H01C29/40

CPC分类号： H01L23/485 ,  H01L21/76801 ,  H01L21/76828 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/12044

摘要： A method and structure for reducing short circuits in semiconductor devices is disclosed. A three layer interlevel dielectric structure is formed over a semiconductor substrate, which typically comprises a first metallization level, M1. The three layer dielectric includes a first insulator layer, a middle spin-on glass (SOG) layer, and a top second insulator layer. The spin-on glass fills defects in the surface of the first insulator layer created during planarization using chemical-mechanical-polishing (CMP). Prior to deposition of the second insulator, a first via is etched through the SOG film and the first insulator layer to expose a portion of the semiconductor substrate, typically a conductive metal. A conductive metal is deposited into the first via and planarized to form a metal interconnection stud. Because the surface defects are filled and covered with the SOG film, none of the deposited metal enters the defects, and short circuits with the stud are greatly reduced. The second insulator layer is deposited onto the SOG film and the end of the metal interconnection stud. A second via is formed through the second insulator material to the stud end, and the second via is available for subsequent deposition of a conductive metal to provide electrical connection to the semiconductor substrate.

摘要翻译： 公开了一种减少半导体器件短路的方法和结构。 在半导体衬底上形成三层层间电介质结构，半导体衬底通常包括第一金属化层M1。 三层电介质包括第一绝缘体层，中间旋涂玻璃（SOG）层和顶部第二绝缘体层。 旋涂玻璃填充使用化学机械抛光（CMP）在平面化期间产生的第一绝缘体层的表面中的缺陷。 在沉积第二绝缘体之前，通过SOG膜和第一绝缘体层蚀刻第一通孔以暴露半导体衬底的一部分，通常为导电金属。 将导电金属沉积到第一通孔中并平坦化以形成金属互连螺柱。 由于表面缺陷被SOG膜填充和覆盖，所以没有沉积的金属进入缺陷，并且螺柱的短路大大降低。 第二绝缘体层沉积在SOG膜和金属互连柱的端部上。 通过第二绝缘体材料形成第二通孔到螺柱端部，并且第二通孔可用于随后沉积导电金属以提供与半导体衬底的电连接。