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1.发明授权Structure for reducing microelectronic short circuits using spin-on glass as part of the interlayer dielectric 失效使用旋涂玻璃作为层间电介质的一部分来减少微电子短路的结构
公开(公告)号：US5710460A
公开(公告)日：1998-01-20
申请号：US426303
申请日：1995-04-21
IPC分类号： H01L21/3205 , H01L21/304 , H01L21/768 , H01L23/485 , H01L23/522 , H01L23/532 , H01L23/48 , H01L23/52 , H01C29/40
CPC分类号： H01L23/485 , H01L21/76801 , H01L21/76828 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/12044
摘要： A method and structure for reducing short circuits in semiconductor devices is disclosed. A three layer interlevel dielectric structure is formed over a semiconductor substrate, which typically comprises a first metallization level, M1. The three layer dielectric includes a first insulator layer, a middle spin-on glass (SOG) layer, and a top second insulator layer. The spin-on glass fills defects in the surface of the first insulator layer created during planarization using chemical-mechanical-polishing (CMP). Prior to deposition of the second insulator, a first via is etched through the SOG film and the first insulator layer to expose a portion of the semiconductor substrate, typically a conductive metal. A conductive metal is deposited into the first via and planarized to form a metal interconnection stud. Because the surface defects are filled and covered with the SOG film, none of the deposited metal enters the defects, and short circuits with the stud are greatly reduced. The second insulator layer is deposited onto the SOG film and the end of the metal interconnection stud. A second via is formed through the second insulator material to the stud end, and the second via is available for subsequent deposition of a conductive metal to provide electrical connection to the semiconductor substrate.
摘要翻译： 公开了一种减少半导体器件短路的方法和结构。 在半导体衬底上形成三层层间电介质结构，半导体衬底通常包括第一金属化层M1。 三层电介质包括第一绝缘体层，中间旋涂玻璃（SOG）层和顶部第二绝缘体层。 旋涂玻璃填充使用化学机械抛光（CMP）在平面化期间产生的第一绝缘体层的表面中的缺陷。 在沉积第二绝缘体之前，通过SOG膜和第一绝缘体层蚀刻第一通孔以暴露半导体衬底的一部分，通常为导电金属。 将导电金属沉积到第一通孔中并平坦化以形成金属互连螺柱。 由于表面缺陷被SOG膜填充和覆盖，所以没有沉积的金属进入缺陷，并且螺柱的短路大大降低。 第二绝缘体层沉积在SOG膜和金属互连柱的端部上。 通过第二绝缘体材料形成第二通孔到螺柱端部，并且第二通孔可用于随后沉积导电金属以提供与半导体衬底的电连接。
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公开(公告)号：US06388337B1
公开(公告)日：2002-05-14
申请号：US09672672
申请日：2000-09-28
IPC分类号： H01L2358
CPC分类号： H01L31/186 , H01L27/148 , H01L31/02162 , H01L2924/0002 , Y02E10/50 , Y02P70/521 , H01L2924/00
摘要： A technique for post-processing a conventionally completed semiconductor device having a final passivation layer and bond pads exposed through the final passivation layer. The technique includes forming a protective film over the final passivation layer and exposed bond pads of the semiconductor device, and thereafter performing post-processing of the completed semiconductor device. Post-process structures, such as charge-coupled devices, can be formed above the protective film during this post-processing. Subsequent to the post-processing, the protective film is selectively etched to again expose the bond pads.
摘要翻译： 一种用于后处理具有最终钝化层的常规完成的半导体器件和通过最终钝化层暴露的接合焊盘的技术。 该技术包括在半导体器件的最终钝化层和暴露的接合焊盘上形成保护膜，然后执行完成的半导体器件的后处理。 在后处理期间，可以在保护膜上形成后处理结构，例如电荷耦合器件。 在后处理之后，选择性地蚀刻保护膜以再次暴露接合焊盘。
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公开(公告)号：US06174824B1
公开(公告)日：2001-01-16
申请号：US09262110
申请日：1999-03-04
IPC分类号： H01L2131
CPC分类号： H01L31/186 , H01L27/148 , H01L31/02162 , H01L2924/0002 , Y02E10/50 , Y02P70/521 , H01L2924/00
摘要： A technique for post-processing a conventionally completed semiconductor device having a final passivation layer and bond pads exposed through the final passivation layer. The technique includes forming a protective film over the final passivation layer and exposed bond pads of the semiconductor device, and thereafter performing post-processing of the completed semiconductor device. Post-process structures, such as charge-coupled devices, can be formed above the protective film during this post-processing. Subsequent to the post-processing, the protective film is selectively etched to again expose the bond pads.
摘要翻译： 一种用于后处理具有最终钝化层的常规完成的半导体器件和通过最终钝化层暴露的接合焊盘的技术。 该技术包括在半导体器件的最终钝化层和暴露的接合焊盘上形成保护膜，然后执行完成的半导体器件的后处理。 在后处理期间，可以在保护膜上形成后处理结构，例如电荷耦合器件。 在后处理之后，选择性地蚀刻保护膜以再次暴露接合焊盘。
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公开(公告)号：US5766808A
公开(公告)日：1998-06-16
申请号：US792408
申请日：1997-01-31
IPC分类号： G03F7/00 , G03F7/038 , H01L21/027 , H01L21/285 , H01L21/60 , H01L21/768 , H05K3/14 , H05K3/34
CPC分类号： G03F7/0387 , G03F7/0035 , H01L21/0272 , H01L21/28512 , H01L21/28562 , H01L21/7688 , H01L24/11 , H01L2224/1147 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1305 , H01L2924/19041 , H01L2924/19043 , H05K3/143 , H05K3/3457
摘要： A process is disclosed for forming multilayered polyimide structure from negative photosensitive polyimide precursors. An initial polyimide layer is deposited and imagewise exposed. The unexposed portions of the initial polyimide layer are inhibited and then a second polyimide layer is deposited and likewise imagewise exposed. The films are developed, thereby forming a multilayer polyimide structure. After formation of the multilayer polyimide structure, a conductive material is applied on a substrate and then the polyimide layers are lifted off thereby forming a desired pattern of metallization.
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公开(公告)号：US5641838A
公开(公告)日：1997-06-24
申请号：US486906
申请日：1995-06-07
IPC分类号： C08L83/06 , C08G73/10 , C08G77/54 , C08L83/02 , C09D183/14 , H01L21/302 , H01L21/3065 , H01L21/312 , C08G77/26
CPC分类号： C09D183/14 , C08G73/106 , C08G73/1082 , C08G77/54 , Y10T428/31663
摘要： Novel intermediate compounds capable of being applied to a semiconductor precursor by spin-on methods which exhibit good planarity and gap-fill characteristics, the cured composites of which are capable of withstanding temperatures in excess of 500.degree. C. The disclosure further encompasses a process for fabricating semiconductor devices utilizing the intermediate compounds and its composite.
摘要翻译： 新型中间体化合物能够通过旋涂方法施加到半导体前体上，所述旋涂方法表现出良好的平整度和间隙填充特性，其固化复合材料能承受超过500℃的温度。本发明还包括一种方法 利用中间体化合物及其复合材料制造半导体器件。
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