公开(公告)号：US5714398A

公开(公告)日：1998-02-03

申请号：US680820

申请日：1996-07-16

申请人： Tien Sheng Chao ,  Horng-Chih Lin

发明人： Tien Sheng Chao ,  Horng-Chih Lin

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/49 ,  H01L21/225 ,  H01L21/255

CPC分类号： H01L29/66515 ,  H01L21/28061 ,  H01L21/823842 ,  H01L29/41783 ,  H01L29/4941 ,  H01L29/66575 ,  H01L29/66545

摘要： The present invention is to develop a proper new process for deep submicron PMOSFET. The characteristic of this process is using Si:Ge:B layer to deposit on the poly-Si film, then go through oxidation or diffusion method to diffuse the boron ion into the poly-Si gate in order to form p-type poly-Si gate. This layer can be etched selectively after spacer etching and reserve a concave gate structure. Thus, it can combine with selective W-CVD to form an excellent p-type poly-Si PMOSFET.

摘要翻译： 本发明是为深亚微米PMOSFET开发适当的新工艺。 该方法的特征是使用Si：Ge：B层沉积在多晶硅膜上，然后通过氧化或扩散方法将硼离子扩散到多晶硅栅中，以便形成p型多晶硅 门。 可以在间隔蚀刻后选择性地蚀刻该层，并且保留凹栅结构。 因此，它可以与选择性W-CVD组合形成优异的p型多晶硅PMOSFET。

公开(公告)号：US5620925A

公开(公告)日：1997-04-15

申请号：US327450

申请日：1994-10-21

申请人： Rempei Nakata ,  Hitoshi Itoh ,  Takashi Endo ,  Tohru Watanabe

发明人： Rempei Nakata ,  Hitoshi Itoh ,  Takashi Endo ,  Tohru Watanabe

IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/255

CPC分类号： H01L21/28525 ,  H01L21/76879

摘要： A method of manufacturing a semiconductor device comprising the steps of forming an insulating layer on a first conductive layer deposited on a semiconductor substrate, treating the surface of the insulating layer and the exposed surface of the first conductive layer with a gas plasma containing halogen atoms, and depositing selectively a conductive material by vapor growth on the exposed surface of the first conductive layer so as to form a second conductive layer. The gas plasma containing halogen atoms can be formed by introducing a gas containing halogen atoms into the treatment chamber housing the sample, and applying high frequency power. The gas plasma containing halogen atoms can be formed by introducing a gas containing halogen atoms into the treatment chamber to adsorb the halogen atoms on the inner wall of the chamber, and applying high frequency power. Alternatively, the gas plasma can be formed by applying high frequency power after placing the sample and a halogen containing material inside the chamber. By treatment with the gas plasma containing halogen atoms, a second conductive layer can be deposited with good selectivity.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在沉积在半导体衬底上的第一导电层上形成绝缘层，用包含卤素原子的气体等离子体处理绝缘层的表面和第一导电层的暴露表面， 以及通过气相生长选择性地沉积在第一导电层的暴露表面上以形成第二导电层的导电材料。 含有卤素原子的气体等离子体可以通过将含有卤素原子的气体引入到容纳样品的处理室中并施加高频功率来形成。 含有卤原子的气体等离子体可以通过将含有卤素原子的气体引入处理室来吸附室内壁上的卤素原子并施加高频功率来形成。 或者，可以在将样品和含卤素材料放置在室内之后施加高频功率来形成气体等离子体。 通过用含有卤原子的气体等离子体处理，可以以良好的选择性沉积第二导电层。

公开(公告)号：US5620911A

公开(公告)日：1997-04-15

申请号：US365293

申请日：1994-12-28

申请人： Sang H. Park

发明人： Sang H. Park

IPC分类号： H01L21/336 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/78 ,  H01L21/265 ,  H01L21/302 ,  H01L21/44 ,  H01L21/255

CPC分类号： H01L29/7834 ,  H01L29/41775 ,  H01L29/456 ,  H01L29/66613

摘要： A method for fabricating a metal oxide semiconductor field effect transistor, capable of achieving a reduction in topology by forming a trench on a silicon substrate by use of a temporary field oxide film and forming a gate electrode in the trench and capable of eliminating occurrence of a spiking phenomenon due to a metal wiring being in direct contact with the silicon substrate by forming a silicide film on a source and a drain, and capable of obtaining an increased contact margin of the metal wiring by overlapping the silicide film with a field oxide film formed on the silicon substrate.

摘要翻译： 一种制造金属氧化物半导体场效应晶体管的方法，其能够通过使用临时场氧化膜在硅衬底上形成沟槽并在沟槽中形成栅电极来实现拓扑的减小，并且能够消除 由于金属布线通过在源极和漏极上形成硅化物膜而与金属布线直接接触，并且能够通过与形成的场氧化膜重叠硅化物膜而获得金属布线的增加的接触边缘，从而引起尖峰现象 在硅衬底上。

公开(公告)号：US5444003A

公开(公告)日：1995-08-22

申请号：US81761

申请日：1993-06-23

申请人： Chung S. Wang ,  Ying-Tsong Loh ,  Ho-Yuan Yu

发明人： Chung S. Wang ,  Ying-Tsong Loh ,  Ho-Yuan Yu

IPC分类号： H01L21/8249 ,  H01L27/06 ,  H01L21/265 ,  H01L21/70 ,  H01L27/00 ,  H01L21/255

CPC分类号： H01L27/0623 ,  H01L21/8249

摘要： A bipolar transistor is fabricated in a CMOS-compatible process so as to be self-aligning, with resultant small geometry and improved high frequency performance, and to have improved hot carrier characteristics. The bipolar device has a laterally graded emitter structure that is fabricated in a "top-down" implant process. During fabrication sidewall spacers are formed overlying the peripheral region of the laterally graded emitter. These spacers protect the underlying region against counter-doping during a subsequent intrinsic base implant, and cause the emitter and base contacts to be self-aligning. Because bipolar dimensions are thus reduced, a very narrow base width is achieved, resulting in improved device cutoff frequency. Further, a narrower emitter-base contact separation is achieved, reducing junction area and attendant junction capacitance. A base link region is formed to further improve emitter-base breakdown voltage, and to reduce extrinsic base resistance. A BiCMOS integrated circuit may be fabricated with bipolar transistors of either polarity and with MOS transistors of either polarity. BiCMOS fabrication can occur wherein substantially the same process steps are employed, or wherein specific bipolar and MOS implant steps are decoupled to optimize laterally graded emitter dopant profiles, base-link resistance, and MOS off-state leakage currents.

摘要翻译： 双极晶体管以CMOS兼容工艺制造，以便进行自对准，从而获得小的几何形状和改善的高频性能，并具有改进的热载流子特性。 双极器件具有横向渐变的发射极结构，其以“自顶向下”植入工艺制造。 在制造期间，侧壁间隔物形成在横向渐变发射体的周边区域上。 这些间隔件在随后的本征基极植入期间保护底层区域免受反掺杂，并且使发射极和基极触点自对准。 因为双极尺寸因此减小，所以实现非常窄的基极宽度，导致器件截止频率的提高。 此外，实现较窄的发射极 - 基极接触分离，减少结面积和伴随的结电容。 形成基极连接区域以进一步提高发射极 - 基极击穿电压，并减少外部基极电阻。 BiCMOS集成电路可以用任一极性的双极晶体管和任一极性的MOS晶体管制造。 可以发生BiCMOS制造，其中采用基本上相同的工艺步骤，或者其中特定的双极和MOS注入步骤被去耦以优化横向渐变的发射极掺杂物分布，基极连接电阻和MOS截止状态漏电流。