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    Non-volatile memory cell and method of programming for improved data retention
    1.
    发明授权
    Non-volatile memory cell and method of programming for improved data retention 失效
    非易失性存储单元和编程方法，用于改进数据保留

    公开(公告)号：US06768160B1

    公开(公告)日：2004-07-27

    申请号：US10352658

    申请日：2003-01-28

    申请人： Yu Li ,  Zhizheng Liu ,  Mark W. Randolph

    发明人： Yu Li ,  Zhizheng Liu ,  Mark W. Randolph

    IPC分类号： H01L29788

    CPC分类号： H01L29/78696 ,  G11C16/0466 ,  H01L27/115 ,  H01L27/1203 ,  H01L29/66833 ,  H01L29/7885 ,  H01L29/792

    摘要： An array of non-volatile memory cells is provided for storing a data pattern and reproducing the data pattern. The array comprises a semiconductor substrate moderately doped with a first type of impurity to enhance conductivity. A plurality of bit lines within the substrate define a plurality of vertical channel regions spaced there between. Each bit line comprises the substrate doped with a second type of impurity to enhance conductivity. Each channel comprises a moderately doped channel region portion adjacent to a first one of the bit lines and a slightly more heavily doped channel region portion adjacent to a second one of the bit lines. A plurality of parallel spaced apart semiconductor word lines are positioned over the substrate and separated from the substrate by an insulator film, a charge storage region, and a second insulator film. An array control circuit is coupled to each bit line and each word line to provide a drain bit line programming potential the second one of the bit line diffusions to accelerating electrons from the first one of the bit line diffusions towards the second one of the bit line diffusions and to provide a word line programming potential to a selected one of the word lines to divert the accelerated electrons from the channel region beneath the selected word line across the insulator film into the charge storage region.

    摘要翻译： 提供了一组非易失性存储器单元，用于存储数据模式并再现数据模式。 该阵列包括适度地掺杂有第一类杂质以增强导电性的半导体衬底。 衬底内的多个位线限定了在其之间间隔开的多个垂直沟道区域。 每个位线包括掺杂有第二类杂质的衬底以增强导电性。 每个通道包括与第一位线相邻的适度掺杂的沟道区域部分和与第二位线相邻的稍高掺杂的沟道区域部分。 多个并联的间隔开的半导体字线位于衬底之上并且通过绝缘膜，电荷存储区和第二绝缘膜与衬底分离。 阵列控制电路耦合到每个位线和每个字线，以提供漏极位线编程电位，位线扩散中的第二个位加速电子从位线扩散中的第一个朝向位线的第二个 并且为所选择的一条字线提供字线编程电位，以将加速电子从所选择的字线下方的沟道区域跨过绝缘膜转移到电荷存储区域中。

    System for programming a non-volatile memory cell
    3.
    发明授权
    System for programming a non-volatile memory cell 有权
    用于编程非易失性存储单元的系统

    公开(公告)号：US06795342B1

    公开(公告)日：2004-09-21

    申请号：US10307667

    申请日：2002-12-02

    申请人： Yi He ,  Zhizheng Liu ,  Mark W. Randolph ,  Sameer S. Haddad

    发明人： Yi He ,  Zhizheng Liu ,  Mark W. Randolph ,  Sameer S. Haddad

    IPC分类号： G11C1604

    CPC分类号： G11C16/10 ,  G11C16/0475 ,  G11C16/0491

    摘要： A system for programming a charge stored on a charge storage region of a dielectric charge trapping layer of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises applying a positive source programming bias to a first bit line that is the source of the selected memory cell while applying a drain programming voltage to a second bit line that forms a drain junction with the channel region and while applying a positive voltage to a selected word line. The source voltage may be applied by coupling the source bit line to a voltage divider or by coupling the source bit line to a resistor which in turn is coupled to a ground. A negative programming bias may also be applied to the substrate and to unselected word lines.

    摘要翻译： 一种用于对存储在双位介质存储器单元阵列内的第一双位介质存储单元的介电电荷俘获层的电荷存储区域上的电荷进行编程的系统包括将正源编程偏置施加到第一位线 同时将漏极编程电压施加到与沟道区形成漏极结的第二位线以及向所选择的字线施加正电压的所选存储单元的源极。 可以通过将源极线耦合到分压器或通过将源极线耦合到电阻器来施加源极电压，电阻器又连接到地电位器。 负编程偏置也可以应用于衬底和未选择的字线。

    Method for reading a non-volatile memory cell
    5.
    发明授权
    Method for reading a non-volatile memory cell 失效
    读取非易失性存储单元的方法

    公开(公告)号：US06795357B1

    公开(公告)日：2004-09-21

    申请号：US10283590

    申请日：2002-10-30

    申请人： Zhizheng Liu ,  Yi He ,  Mark W. Randolph ,  Sameer S. Haddad

    发明人： Zhizheng Liu ,  Yi He ,  Mark W. Randolph ,  Sameer S. Haddad

    IPC分类号： G11C700

    CPC分类号： G11C16/0491 ,  G11C16/0475 ,  G11C16/26

    摘要： A method of detecting a charge stored on a charge storage region of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises applying a source voltage to a first bit line that is the source of the selected memory cell and applying a drain voltage to a second bit line that forms a drain junction with the channel region. The source voltage may be a small positive voltage and the drain voltage may be greater than the source voltage. A read voltage is applied to a selected one of the word lines that forms a gate over the charge storage region and a bias voltage is applied to non-selected word lines in the array. The bias voltage may be a negative voltage.

    摘要翻译： 检测存储在双位介质存储器单元阵列内的第一双位介质存储单元的电荷存储区域上的电荷的方法包括将源电压施加到作为所选存储单元的源的第一位线并施加 到与沟道区形成漏极结的第二位线的漏极电压。 源极电压可以是小的正电压，并且漏极电压可能大于源极电压。 将读取电压施加到在电荷存储区域上形成栅极的所选择的一条字线，并且将偏置电压施加到阵列中的未选择的字线。 偏置电压可以是负电压。

    Pre-charge method for reading a non-volatile memory cell
    6.
    发明授权
    Pre-charge method for reading a non-volatile memory cell 失效
    用于读取非易失性存储单元的预充电方法

    公开(公告)号：US06788583B2

    公开(公告)日：2004-09-07

    申请号：US10307749

    申请日：2002-12-02

    申请人： Yi He ,  Edward F. Runnion ,  Zhizheng Liu ,  Mark W. Randolph ,  Darlene G. Hamilton ,  Pauling Chen ,  Binh Le

    发明人： Yi He ,  Edward F. Runnion ,  Zhizheng Liu ,  Mark W. Randolph ,  Darlene G. Hamilton ,  Pauling Chen ,  Binh Le

    IPC分类号： G11C1606

    CPC分类号： G11C7/12 ,  G11C16/0475 ,  G11C16/24

    摘要： A method of detecting a charge stored on a charge storage region of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises grounding a first bit line that forms a source junction with a channel region of the first memory cell. A high voltage is applied to a gate of the first memory cell and to a second bit line that is the next bit line to the right of the first bit line and separated from the first bit line only by the channel region. A third bit line, that is the next bit line to the right of the second bit line, is isolated such that its potential is effected only by its junctions with the a second channel region and a third channel region on opposing sides of the third bit line. A high voltage is applied to a pre-charge bit line that is to the right of the third bit line and current flow is detected at the second bit line to determine the programmed status of a source bit of the memory cell.

    摘要翻译： 一种检测存储在双位介质存储器单元阵列内的第一双位介质存储单元的电荷存储区域上的电荷的方法包括使与第一存储单元的沟道区形成源极结的第一位线接地。 高电压被施加到第一存储单元的栅极和第二位线，第二位线是第一位线右侧的下一个位线，并且仅与通道区域从第一位线分离。 位于第二位线右侧的下一个位线的第三位线是隔离的，使得其电位仅由其与第二通道区域的结和仅在第三位的相对侧上的第三通道区域 线。 将高电压施加到位于第三位线右侧的预充电位线，并且在第二位线处检测电流以确定存储器单元的源位的编程状态。

    Overerase correction method
    9.
    发明授权
    Overerase correction method 有权
    过度修正方法

    公开(公告)号：US06639844B1

    公开(公告)日：2003-10-28

    申请号：US10099499

    申请日：2002-03-13

    申请人： Zhizheng Liu ,  Yi He ,  Mark W. Randolph

    发明人： Zhizheng Liu ,  Yi He ,  Mark W. Randolph

    IPC分类号： G11C1604

    CPC分类号： G11C16/3409 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/3404 ,  G11C16/344

    摘要： A method for correcting overerasure in a multi-bit memory device. A sector of multi-bite memory cells in the device is erased and verified. After erase and verification, the overerased memory cells are soft programmed and verified to correct for overerasure. A soft programming pulse with a Vg to Vd ratio (Vg/Vd) greater than or equal to two is used.

    摘要翻译： 一种用于在多位存储器件中校正过度曝光的方法。 器件中的多点存储器单元的扇区被擦除和验证。 在擦除和验证之后，过高的存储单元被软编程并被验证以校正过高。 使用Vg至Vd比（Vg / Vd）大于或等于2的软编程脉冲。