Time borrowing using dynamic clock shift for bus speed performance
    1.
    发明授权
    Time borrowing using dynamic clock shift for bus speed performance 失效
    时间借用动态时钟转换为总线速度性能

    公开(公告)号:US06803783B2

    公开(公告)日:2004-10-12

    申请号:US10355559

    申请日:2003-01-31

    IPC分类号: H03K1706

    CPC分类号: G06F13/4291

    摘要: An apparatus and method for increasing the performance of a common-clock data bus is provided by borrowing time from the common-clock domain timing. The time may be borrowed by dynamically delaying the common-clock before providing it to a receiving path. In a system comprising a plurality of logic devices electrically coupled to a data bus, time may be borrowed from the internal common-clock timing domain of one of the plurality of logic devices when receiving data through the data bus from an external logic device. To prevent race conditions, a logic device of the plurality of logic devices may be configured to switch off the time borrowing when receiving data from an internal driving path. To avoid glitches, the logic device may be configured to switch the time borrowing feature on and off only at select time intervals.

    摘要翻译: 通过从公共时钟域定时借用时间来提供用于增加公共时钟数据总线的性能的装置和方法。 可以在将公共时钟提供给接收路径之前动态地延迟公共时钟来借用该时间。 在包括电耦合到数据总线的多个逻辑器件的系统中,当从外部逻辑器件接收数据通过数据总线时,可以从多个逻辑器件之一的内部公共时钟定时域借入时间。 为了防止竞争条件,多个逻辑设备的逻辑设备可以被配置为在从内部驱动路径接收数据时关闭借用时间。 为了避免毛刺,逻辑器件可以被配置为仅在选定的时间间隔开启和关闭时间借用功能。