公开(公告)号：US06882201B1

公开(公告)日：2005-04-19

申请号：US10754075

申请日：2004-01-07

申请人： Kenneth Koch, II ,  Manuel Cabanas-Holmen ,  Daniel W. Krueger

发明人： Kenneth Koch, II ,  Manuel Cabanas-Holmen ,  Daniel W. Krueger

IPC分类号： H03K3/037 ,  H03K3/356

CPC分类号： H03K3/0375

摘要： In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch. An input driver is connected to the input of two transfer gates. The output of one transfer gate is connected to an I/O of a first latch and the output of the second transfer gate is connected to the I/O of a second latch. The I/O of the first latch is connected to a first input of a tristatable input inverter. The I/O of the second latch is connected to a second input of the tristatable input inverter. The output of the tristatable input inverter is connected to the I/O of a third latch and the input of an output driver.

摘要翻译： 在优选实施例中，本发明提供了一种用于更小和更快的三重冗余锁存器的电路和方法。 输入驱动器连接到两个传输门的输入端。 一个传输门的输出连接到第一锁存器的I / O，第二传输门的输出端连接到第二锁存器的I / O。 第一锁存器的I / O连接到可跟踪输入反相器的第一输入端。 第二锁存器的I / O连接到可跟踪输入反相器的第二输入端。 可跟踪输入反相器的输出端连接到第三个锁存器的I / O和输出驱动器的输入端。

公开(公告)号：US06753708B2

公开(公告)日：2004-06-22

申请号：US10167493

申请日：2002-06-13

申请人： Kenneth Koch, II ,  Mozammel Hossain

发明人： Kenneth Koch, II ,  Mozammel Hossain

IPC分类号： H03B100

CPC分类号： H03K19/0013 ,  H03K17/08122 ,  H03K17/163

摘要： An integrated circuit driver includes an output stage having source drain paths of a PFET and NFET connected in series with each other across DC power supply terminals. A pair of inverters simultaneously responsive to a bilevel signal drive gate electrodes of the PFET and NFET. Each inverter includes a pair of switches and a resistor for connecting opposite polarity voltage sources to a separate capacitor connected in shunt with gate electrodes of the PFET and NFET. The inverters, resistors and capacitors prevent the PFET and NFET from being on simultaneously.

摘要翻译： 集成电路驱动器包括具有在直流电源端子上彼此串联连接的PFET和NFET的源极漏极路径的输出级。 一对逆变器同时响应PFET和NFET的双电平信号驱动栅电极。 每个逆变器包括一对开关和电阻器，用于将反极性电压源连接到与PFET和NFET的栅电极并联连接的单独电容器。 逆变器，电阻和电容器可以防止PFET和NFET同时导通。

公开(公告)号：US06404243B1

公开(公告)日：2002-06-11

申请号：US09759718

申请日：2001-01-12

申请人： Kenneth Koch, II ,  William Weiner

发明人： Kenneth Koch, II ,  William Weiner

IPC分类号： H03B2100

CPC分类号： H03K5/159 ,  H03K5/133 ,  H03K19/0013 ,  H03K19/01707 ,  H03K2005/00136

摘要： The present invention discloses a floating body architecture CMOSFET inverter with body biasing inverters added for controlling the delay time of the inverter. At least one body biasing inverter is connected between the main inverter's input and the body terminals of the FETs of the inverter. By supplying a representation of the input voltage to the body terminals of the p-channel and n-channel FETs, the preferred embodiment of the present invention is able to control the history dependent delay time associated with the variable source-to-body voltages in floating body CMOSFET inverters. The delay time is minimized by adding an odd number of body biasing inverter stages into the main inverter circuit. The delay time can also be maximized by adding an even number of body biasing inverter stages into the circuit.

摘要翻译： 本发明公开了一种用于控制逆变器的延迟时间的体积偏置逆变器的浮体结构CMOSFET逆变器。 在主逆变器的输入端和变频器的FET的主体端子之间连接有至少一个主体偏置逆变器。 通过向p沟道和n沟道FET的体式端子提供输入电压的表示，本发明的优选实施例能够控制与可变源极对体电压相关联的与历史相关的延迟时间 浮体CMOSFET逆变器。 通过向主逆变器电路中添加奇数个体偏置反相器级来延迟时间被最小化。 通过在电路中添加偶数个体偏置反相器级，延迟时间也可以最大化。

公开(公告)号：US07433426B2

公开(公告)日：2008-10-07

申请号：US10831095

申请日：2004-04-23

申请人： Zhubiao Zhu ,  Kenneth Koch, II ,  David J. C. Johnson

发明人： Zhubiao Zhu ,  Kenneth Koch, II ,  David J. C. Johnson

IPC分类号： H03K9/00 ,  H04L27/00

CPC分类号： H04L25/063 ,  H03K5/082 ,  H03K5/1252

摘要： An adaptive hysteresis receiver processes a high speed digital signal. A differential receiver circuit compares the high speed digital signal to a reference voltage to generate an output signal. A register circuit latches the output signal, according to a clock signal, to produce a control signal. A reference voltage generator generates the reference voltage, from a plurality of voltages defining a deep hysteresis level and a shallow hysteresis level, in response to the output signal and the control signal.

摘要翻译： 自适应迟滞接收器处理高速数字信号。 差分接收器电路将高速数字信号与参考电压进行比较以产生输出信号。 寄存器电路根据时钟信号锁存输出信号以产生控制信号。 参考电压发生器响应于输出信号和控制信号从限定深滞后电平和浅滞后电平的多个电压产生参考电压。

公开(公告)号：US20070168886A1

公开(公告)日：2007-07-19

申请号：US11694482

申请日：2007-03-30

申请人： J. Hally ,  Kenneth Koch ,  Mark Ligameri ,  Jason Moore ,  Shaun Kaasten ,  Richard Banks ,  Michael Sheldon ,  David De Vorchik ,  Zeke Odins-Lucas ,  Patrice Miner

发明人： J. Hally ,  Kenneth Koch ,  Mark Ligameri ,  Jason Moore ,  Shaun Kaasten ,  Richard Banks ,  Michael Sheldon ,  David De Vorchik ,  Zeke Odins-Lucas ,  Patrice Miner

IPC分类号： G06F3/048

CPC分类号： G06F3/04842 ,  G06F3/0481

摘要： A virtual address bar user interface control is presented. The virtual address bar includes a plurality of interactive segments, each segment corresponding to a predetermined filter for selecting content in a computer file system. Collectively, the interactive segments represent a virtual address for selecting content. Selecting an interactive segment in the virtual address bar causes those segments subsequent to the selected segment to be removed from the virtual address bar. A user may select a peer filter for a segment to replace that segment's current filter and removes those segments subsequent to the updated segment. The virtual address bar can be selectively configured to operate as a conventional address bar, and reconfigured to operate as a virtual address bar. Additional filter segments are added to the end of the existing filter segments. Those existing filter segments that conflict with the added segment are removed from the virtual address bar.

摘要翻译： 呈现虚拟地址栏用户界面控件。 虚拟地址栏包括多个交互式段，每个段对应于用于在计算机文件系统中选择内容的预定过滤器。 总体上，交互式段代表用于选择内容的虚拟地址。 在虚拟地址栏中选择一个交互式区段会使选定段后面的区段从虚拟地址栏中移除。 用户可以为段选择对等体过滤器来替换该段的当前过滤器并且去除更新段之后的那些段。 虚拟地址栏可以被选择性地配置为作为常规地址栏操作，并且被重新配置为作为虚拟地址栏操作。 额外的过滤器段被添加到现有过滤段的末端。 那些与添加的段冲突的现有过滤器段从虚拟地址栏中删除。

公开(公告)号：US20060234190A1

公开(公告)日：2006-10-19

申请号：US11396382

申请日：2006-03-31

申请人： Kenneth Koch ,  Dennis Brave

发明人： Kenneth Koch ,  Dennis Brave

IPC分类号： A61C5/02 ,  A61C5/08

CPC分类号： A61C13/30 ,  A61C5/40 ,  A61C5/50 ,  A61C5/70 ,  A61C19/041

摘要： A glass ionomer or resin modified glass ionomer coated blank is combined with glass ionomer or resin modified glass ionomer to create an integral mono-block post. prefabricated glass ionomer or resin modified glass ionomer post (with or without a coated blank) is cemented into the root canal with glass ionomer or resin modified glass ionomer, thereby creating a mono-block post as well as a mono-block core. The glass ionomer or resin modified glass ionomer cement is bonded to the canal wall and also through the bonding of the cement to the post surface of similar material. An alternate methodology involves syringing glass ionomer or resin modified glass ionomer in a malleable, semi-solid state into the post preparation space and a glass ionomer or resin modified glass ionomer coated blank is then inserted into the canal to a distance substantially equal to the depth of the post preparation.

摘要翻译： 将玻璃离子交联聚合物或树脂改性的玻璃离聚物涂布的坯料与玻璃离子交联聚合物或树脂改性的玻璃离聚物组合以产生整体的单嵌段。 用玻璃离子交联聚合物或树脂改性玻璃离聚物将预制玻璃离子交联聚合物或树脂改性的玻璃离聚物柱（有或无涂层坯料）胶合到根管中，从而形成单块柱以及单嵌段核。 玻璃离子交联聚合物或树脂改性的玻璃离子交联聚合物粘合剂结合到管壁上，并且还通过将粘合剂粘合到类似材料的后表面。 一种替代方法包括将可塑性半固体状态的玻璃离聚物或树脂改性的玻璃离子交联聚合物注入到后制备空间中，然后将玻璃离聚物或树脂改性的玻璃离子交联聚合物涂覆的坯料插入到管中至基本等于深度 的后期准备。

公开(公告)号：US07097455B2

公开(公告)日：2006-08-29

申请号：US10744640

申请日：2003-12-22

申请人： Kenneth Koch ,  Dennis Brave ,  William McHale

发明人： Kenneth Koch ,  Dennis Brave ,  William McHale

IPC分类号： A61C5/02

CPC分类号： A61C5/50 ,  A61C5/40

摘要： An integral, one-piece silanated particle impregnated gutta percha core/cone technique employs a thin layer of a luting agent, such as glass ionomer cement with a machined gutta percha core/cone, precisely matches the preparation, thereby reducing leakage and achieving a hermetic seal. The hermetic seal is further enhanced by a mono-block bond that occurs between the silanated particles in the gutta percha and the appropriate chemical sealant. Optional cryogenic treatment of the gutta percha material changes its molecular weight, making it stiffer and conducive to forming an integral, one piece core/cone, without the need for a separate carrier core to install the tapered gutta percha core/cone within the root canal. Additionally, the tapered body of the core/cone may be reticulated in a slightly three dimensional texturized framework to increase surface area and therefore increase retention. Optional line demarcation indicia are also placed on the core/cone. Additionally, the head of the core/cone can be gripped by a delivery vehicle clasp.

摘要翻译： 一体化的单件硅烷化颗粒浸渍的gutta percha芯/锥技术采用薄层的搪瓷剂，例如玻璃离子交联聚合物水泥与加工的gutta percha芯/锥，精确匹配制剂，从而减少渗漏并实现气密 密封。 通过在gutta percha中的硅烷化颗粒和适当的化学密封剂之间发生的单嵌段键进一步增强气密密封。 对牙釉质材料的可选低温处理改变其分子量，使其更硬并且有助于形成整体的一体式芯/锥体，而不需要单独的载体芯将锥形牙髓核/锥体安装在根管内 。 此外，芯/锥体的锥形体可以在稍微三维结构化的框架中网状化以增加表面积并因此增加保持力。 可选的线分界标记也放在核心/锥体上。 此外，芯/锥体的头部可以由输送车钩扣住。

公开(公告)号：US20050127947A1

公开(公告)日：2005-06-16

申请号：US10732687

申请日：2003-12-10

申请人： Barry Arnold ,  Kenneth Koch ,  Philip Barnes

发明人： Barry Arnold ,  Kenneth Koch ,  Philip Barnes

IPC分类号： H03K19/003 ,  H03K19/00

CPC分类号： H03K19/00384

摘要： A signal generated by circuitry for an output buffer is identified relative to a clock signal to control a slew rate of the circuitry for an output buffer.

摘要翻译： 由输出缓冲器的电路产生的信号相对于时钟信号被识别，以控制用于输出缓冲器的电路的转换速率。

公开(公告)号：US06734709B1

公开(公告)日：2004-05-11

申请号：US10383127

申请日：2003-03-06

申请人： Zhubiao Zhu ,  Kenneth Koch, II ,  J Robert Sims, III

发明人： Zhubiao Zhu ,  Kenneth Koch, II ,  J Robert Sims, III

IPC分类号： H03K3017

CPC分类号： G11C27/02 ,  H03K5/04 ,  H03K5/135

摘要： A method and system for sampling on the fly one or more integrated circuit nodes coupled to one or more bus domain clocks of an integrated circuit using minimal clock cycle delay synchronization. Sample on the fly circuitry, set-reset circuitry and metastable rejection circuitry are used to provide a sufficient pulse width for sampling on the fly the one or more nodes when the one or more bus domain clocks require asynchronous operation. The sample on the fly circuitry is also operable to synchronously sample on the fly the one or more nodes.

摘要翻译： 一种用于使用最小时钟周期延迟同步在一个或多个集成电路节点上采集集成电路的一个或多个总线域时钟的方法和系统。 当一个或多个总线域时钟需要异步操作时，在飞行电路，设置复位电路和亚稳态抑制电路上的采样用于提供足够的脉冲宽度用于在一个或多个节点上飞行时进行采样。 飞行电路上的采样也可用于在一个或多个节点上同时采样。

公开(公告)号：US20060154213A1

公开(公告)日：2006-07-13

申请号：US11374629

申请日：2006-03-13

申请人： Kenneth Koch ,  Dennis Brave

发明人： Kenneth Koch ,  Dennis Brave

IPC分类号： A61C5/02

CPC分类号： A61C5/50

摘要： An integral, one-piece gutta percha core/cone technique employs a thin layer of a luting agent, such as glass ionomer cement with a machined gutta percha core/cone, precisely matches the preparation, thereby reducing leakage and achieving a hermetic seal. Optional cryogenic treatment of the gutta percha material changes its molecular weight, making it stiffer and conducive to forming an integral, one piece core/cone, without the need for a separate carrier core to install the tapered gutta percha core/cone within the root canal. Additionally, the tapered body of the core/cone may be reticulated in a slightly three dimensional texturized framework to increase surface area and therefore increase retention. Optional line demarcation indicia are also placed on the core/cone. Additionally, the head of the core/cone can be gripped by a delivery vehicle clasp.

摘要翻译： 整体的单件gutta percha核心/锥形技术采用薄层的搪瓷剂，例如玻璃离聚物水泥与加工的gutta percha芯/锥，精确匹配制剂，从而减少泄漏并实现气密密封。 对牙釉质材料的可选低温处理改变其分子量，使其更硬并且有助于形成整体的一体式芯/锥体，而不需要单独的载体芯将锥形牙髓核/锥体安装在根管内 。 此外，芯/锥体的锥形体可以在稍微三维结构化的框架中网状化以增加表面积并因此增加保持力。 可选的线分界标记也放在核心/锥体上。 此外，芯/锥体的头部可以由输送车钩扣住。