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12 条记录 (耗时 0.021 秒)

    Dual rail power supply sequence tolerant off-chip driver
    5.
    发明授权
    Dual rail power supply sequence tolerant off-chip driver 有权

    公开(公告)号：US06570401B2

    公开(公告)日：2003-05-27

    申请号：US09758054

    申请日：2001-01-10

    申请人： Anthony Correale, Jr. ,  Terry Cain Coughlin, Jr. ,  Douglas Willard Stout

    发明人： Anthony Correale, Jr. ,  Terry Cain Coughlin, Jr. ,  Douglas Willard Stout

    IPC分类号： H03K19007

    CPC分类号： H03K19/00315

    摘要： The protection circuit of the present invention addresses the problem of indeterminate logic levels caused by loss of one of the power supplies in a two-power-supply CMOS integrated circuit. The circuit of the present invention replaces the typical scheme of power supply sequencing to fix the problem. The circuit disclosed herein detects the state of the core voltage and disables the output drivers when the core voltage is detected as being off. The disabled drivers are put into a high impedance state, thereby eliminating the potential for damage and eliminating the need for power supply sequencing. The invention also protects against the sudden loss of the integrated circuit core voltage, VDD, power supply during normal operation.

    Off-chip driver for mixed voltage applications
    8.
    发明授权
    Off-chip driver for mixed voltage applications 失效
    用于混合电压应用的片外驱动器

    公开(公告)号：US5644265A

    公开(公告)日：1997-07-01

    申请号：US431882

    申请日：1995-05-01

    申请人： John Stephen Austin ,  Douglas Willard Stout

    发明人： John Stephen Austin ,  Douglas Willard Stout

    IPC分类号： H01L21/8234 ,  H01L27/088 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/0944 ,  H03L5/00

    CPC分类号： H03K19/018521 ,  H03K19/00315 ,  H03K19/01721

    摘要： A level shifting driver shifts a low magnitude logic signal to a high magnitude logic signal while preventing a high supply voltage as associated with the high magnitude logic signal from feeding back into logic devices associated with providing the low magnitude logic signal. An input terminal receives the low magnitude logic signal from a given low voltage logic device. An N-channel MOSFET has its channel disposed serially between the input terminal and an output terminal and its gate coupled to a low supply voltage of the low voltage logic device. A latch network biased by the high supply voltage has one node of its latch coupled to the output terminal for providing an output signal representative of the low magnitude logic signal but of a high magnitude established in accordance with the high supply voltage.

    摘要翻译： 电平移位驱动器将低幅度逻辑信号移位到高幅度逻辑信号，同时防止与高幅度逻辑信号相关联的高电源电压反馈到与提供低幅度逻辑信号相关联的逻辑器件。 输入端子从给定的低电压逻辑器件接收低幅度逻辑信号。 N沟道MOSFET的通道串联设置在输入端和输出端之间，其栅极耦合到低电压逻辑器件的低电源电压。 由高电源电压偏置的锁存网络具有其锁存器的一个节点耦合到输出端子，用于提供表示低幅度逻辑信号但是具有根据高电源电压建立的高电平的输出信号。

    Circuits to reduce threshold voltage tolerance and skew in multi-threshold voltage applications
    9.
    发明授权
    Circuits to reduce threshold voltage tolerance and skew in multi-threshold voltage applications 有权
    降低多阈值电压应用中阈值电压容限和偏斜的电路

    公开(公告)号：US07459958B2

    公开(公告)日：2008-12-02

    申请号：US11424961

    申请日：2006-06-19

    申请人： Corey Kenneth Barrows ,  Douglas W. Kemerer ,  Stephen Gerard Shuma ,  Douglas Willard Stout ,  Oscar Conrad Strohacker ,  Mark Steven Styduhar ,  Paul Steven Zuchowski

    发明人： Corey Kenneth Barrows ,  Douglas W. Kemerer ,  Stephen Gerard Shuma ,  Douglas Willard Stout ,  Oscar Conrad Strohacker ,  Mark Steven Styduhar ,  Paul Steven Zuchowski

    IPC分类号： H03K3/01

    CPC分类号： G06F17/5063 ,  H01L27/088 ,  H01L27/092

    摘要： A circuit and a method for adjusting the performance of an integrated circuit, the circuit includes: first and second sets of FETs having respective first and second threshold voltages, the first threshold voltage different from the second threshold voltage; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit adapted to generate a compare signal based on a performance measurement of the first monitor circuit and a performance measurement of the second monitor circuit; and a control unit adapted to generate a control signal to a voltage regulator based on the compare signal, the voltage regulator adapted to supply a bias voltage to wells of FETs of the second set of FETs, the value of the bias voltage based on the control signal.

    摘要翻译： 一种用于调整集成电路性能的电路和方法，所述电路包括：具有相应的第一和第二阈值电压的第一和第二组FET，所述第一阈值电压不同于所述第二阈值电压; 包含第一组FET的至少一个FET的第一监视器电路和包含第二组FET的至少一个FET的第二监视电路; 比较电路，其适于基于第一监视电路的性能测量和第二监视电路的性能测量来产生比较信号; 以及控制单元，其适于基于所述比较信号向所述电压调节器产生控制信号，所述电压调节器适于向所述第二组FET的FET的阱提供偏置电压，所述偏置电压的值基于所述控制 信号。