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    Field programmable memory array
    3.
    发明授权
    Field programmable memory array 失效
    现场可编程存储阵列

    公开(公告)号：US06233191B1

    公开(公告)日：2001-05-15

    申请号：US09510326

    申请日：2000-02-22

    申请人： Scott Whitney Gould ,  Joseph Andrew Iadanza ,  Frank Ray Keyser, III

    发明人： Scott Whitney Gould ,  Joseph Andrew Iadanza ,  Frank Ray Keyser, III

    IPC分类号： G11C700

    CPC分类号： G06F7/785 ,  G06F5/10 ,  G11C7/1006 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/12 ,  G11C8/00 ,  H03K19/17704 ,  H03K19/1776

    摘要： A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.

    摘要翻译： 提供具有多个子阵列的现场可编程存储器阵列。 提供可编程地址解码器，可编程分层位线布置，可编程I / O布置等功能，以使阵列的部分能够编程成选定的模式。 这些模式可以包括宽存储器，深存储器，FIFO，LIFO等。 公开了本发明的实施例，其中现场可编程存储器阵列与现场可编程门阵列的可编程资源集成。

    Programmable logic cell
    5.
    发明授权
    Programmable logic cell 失效
    可编程逻辑单元

    公开(公告)号：US5748009A

    公开(公告)日：1998-05-05

    申请号：US707840

    申请日：1996-09-09

    申请人： Allan Robert Bertolet ,  Kim P. N. Clinton ,  Christine Marie Fuller ,  Scott Whitney Gould ,  Steven Paul Hartman ,  Joseph Andrew Iadanza ,  Frank Ray Keyser ,  Eric Ernest Millham ,  Timothy Shawn Reny ,  Brian A. Worth ,  Gulson Yasar ,  Terrance John Zittritsch

    发明人： Allan Robert Bertolet ,  Kim P. N. Clinton ,  Christine Marie Fuller ,  Scott Whitney Gould ,  Steven Paul Hartman ,  Joseph Andrew Iadanza ,  Frank Ray Keyser ,  Eric Ernest Millham ,  Timothy Shawn Reny ,  Brian A. Worth ,  Gulson Yasar ,  Terrance John Zittritsch

    IPC分类号： H03K19/177 ,  H03K19/173

    CPC分类号： H03K19/1737

    摘要： A programmable logic cell has four logic gates, two of which are configurable. The two configurable logic gates are positioned near the logic cell inputs. Each configurable logic gate has two inputs, each input being connected to one of the four logic cell inputs. The remaining two logic gates receive the outputs of the configurable logic gates. Four independent logic cell input nodes are provided, each having associated therewith a programmable input multiplexer. Each input multiplexer can have inputs connected to at least two types of interconnect conductors. The cell also has two output paths, each having associated therewith an independently-controlled output multiplexer. The output of each output multiplexer is connected to an input of the other output multiplexer. Additional features include a multiplexer having inputs connected to two cell input nodes, a select input connected to a third logic cell input node, and an output connected to a cell output node; a system low-skew data (e.g., clock) input available to at least one of the input multiplexers; a flip-flop connected within the logic cell; and internal cell feedback. The preferred method of programming utilizes user-programmed SRAM memory cells.

    摘要翻译： 可编程逻辑单元具有四个逻辑门，其中两个可配置。 两个可配置逻辑门位于逻辑单元输入附近。 每个可配置逻辑门具有两个输入，每个输入连接到四个逻辑单元输入之一。 剩余的两个逻辑门接收可配置逻辑门的输出。 提供四个独立的逻辑单元输入节点，每个具有与可编程输入多路复用器相关联的逻辑单元输入节点。 每个输入多路复用器可以具有连接到至少两种类型的互连导体的输入。 该单元还具有两个输出路径，每个输出路径与其相关联，具有独立控制的输出多路复用器。 每个输出多路复用器的输出连接到另一个输出多路复用器的输入端。 附加特征包括具有连接到两个单元输入节点的输入的多路复用器，连接到第三逻辑单元输入节点的选择输入和连接到单元输出节点的输出; 用于至少一个输入多路复用器的系统低偏移数据（例如，时钟）输入; 连接在逻辑单元内的触发器; 和内部单元反馈。 优选的编程方法利用用户编程的SRAM存储单元。

    Programmable array interconnect latch
    6.
    发明授权
    Programmable array interconnect latch 失效
    可编程阵列互连锁存器

    公开(公告)号：US5732246A

    公开(公告)日：1998-03-24

    申请号：US480639

    申请日：1995-06-07

    申请人： Scott Whitney Gould ,  Frank Ray Keyser, III ,  Wendell Ray Larsen ,  Brian Allen Worth

    发明人： Scott Whitney Gould ,  Frank Ray Keyser, III ,  Wendell Ray Larsen ,  Brian Allen Worth

    IPC分类号： H03K19/173 ,  G01R31/3185 ,  H03K3/037 ,  H03K19/177 ,  G06F9/455 ,  G06F17/50

    CPC分类号： G01R31/318519 ,  H03K19/17704 ,  H03K19/17748 ,  H03K3/0375

    摘要： A given interconnect of a programmable gate array includes a programmable repeater circuit that enables selective isolation and testing of a select block of configured circuitry within the programmable gate array. The programmable repeater circuit includes an input node coupled to a first portion of the given interconnect and an output node coupled to a second portion of the given interconnect. A selective buffer circuit selectively outputs a buffered output signal to the output node that is related to a logic state at the input node. A signal storage circuit is also connected to the input node for selectively storing the logic state received from the input node. In a further embodiment, the signal storage circuit comprises an LSSD register. A primary latch of the LSSD register receives data selectively either from the input node, in accordance with a first clock signal, or alternatively from a secondary serial input node, in accordance with a second clock signal. A secondary latch of the LSSD register is selectively coupled, per a third clock signal, to receive and latch therein latched data of the primary latch. Data representative of data latched within the secondary latch is provided at a secondary serial output, and selectively provided at the primary output node when enabled per a programmable enable signal. In yet a further embodiment, the LSSD register is part of a serial scan chain for selectively interfacing an interconnect boundary of the select block of the configured circuitry within the programmable gate array.

    摘要翻译： 可编程门阵列的给定互连包括可编程中继器电路，其实现对可编程门阵列内的配置电路的选择块的选择性隔离和测试。 可编程中继器电路包括耦合到给定互连的第一部分的输入节点和耦合到给定互连的第二部分的输出节点。 选择性缓冲电路有选择地将缓冲的输出信号输出到与输入节点处的逻辑状态相关的输出节点。 信号存储电路也连接到输入节点，用于选择性地存储从输入节点接收的逻辑状态。 在另一实施例中，信号存储电路包括LSSD寄存器。 根据第二时钟信号，LSSD寄存器的主锁存器根据第一时钟信号，或者备选地从辅助串行输入节点选择性地从输入节点接收数据。 每个第三时钟信号选择性地耦合LSSD寄存器的辅助锁存器，以在其中接收并锁存主锁存器的锁存数据。 在辅助锁存器中锁存的数据的数据被提供在次级串行输出端，并且当每个可编程使能信号使能时，被选择地提供在主输出节点处。 在又一个实施例中，LSSD寄存器是串行扫描链的一部分，用于选择性地接合可编程门阵列内的配置电路的选择块的互连边界。

    Field programmable gate arrays using semi-hard multicell macros
    8.
    发明授权
    Field programmable gate arrays using semi-hard multicell macros 失效
    使用半硬多核宏的现场可编程门阵列

    公开(公告)号：US5761078A

    公开(公告)日：1998-06-02

    申请号：US618060

    申请日：1996-03-21

    申请人： Christine Marie Fuller ,  Scott Whitney Gould ,  Steven Paul Hartman ,  Eric Ernest Millham ,  Gulsun Yasar

    发明人： Christine Marie Fuller ,  Scott Whitney Gould ,  Steven Paul Hartman ,  Eric Ernest Millham ,  Gulsun Yasar

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： A computer implemented method for the automated placement and routing in the design of field programmable gate arrays achieves optimal timing. In a library of primitives and macros from which a designer may choose to implement a given circuit design, at least some of said macros are "semi-hard" macros where direct connections and relative placements are specified while local bus routing is requested in a manner that does not restrict macro placement. A logical netlist containing references to macros and how to connect them together to perform a logical function is first created. The logical netlist is then translated to a physical netlist using a mapper function. This physical netlist for the semi-hard macros specifies what is to be connected but not how. The best place to put each macro on the field programmable gate array is found using a placer function. The placer function thus determines an absolute position of the macros. Pre-defined macro direct connections are routed using a router function. The router function determines an optimal path to connect the semi-hard macros. Finally, a bitstream is generated from placement and routing information developed by the placer and router functions to program the field programmable gate array to perform the netlist logical function.

    摘要翻译： 用于现场可编程门阵列设计中的自动放置和布线的计算机实现方法实现了最佳的定时。 在设计者可以选择实现给定电路设计的原语和宏的库中，至少一些所述宏是“半硬”宏，其中指定了直接连接和相对放置，同时以某种方式请求本地总线路由 这不会限制宏放置。 首先创建包含对宏的引用以及如何将它们连接在一起以执行逻辑功能的逻辑网表。 然后使用映射器函数将逻辑网表转换为物理网表。 这个半硬宏的物理网表指定了要连接的内容，但不是如何。 使用放置功能可以找到将每个宏放在现场可编程门阵列上的最佳位置。 因此，放置函数决定宏的绝对位置。 使用路由器功能路由预定义的宏直连。 路由器功能确定连接半硬宏的最佳路径。 最后，由放置器和路由器开发的放置和路由信息生成比特流，以对现场可编程门阵列进行编程以执行网表逻辑功能。

    System for enhanced drive in programmable gate arrays
    10.
    发明授权
    System for enhanced drive in programmable gate arrays 失效
    可编程门阵列增强驱动系统

    公开(公告)号：US5694057A

    公开(公告)日：1997-12-02

    申请号：US644382

    申请日：1996-05-10

    申请人： Scott Whitney Gould

    发明人： Scott Whitney Gould

    IPC分类号： H03K19/173 ,  H03K19/0175 ,  H03K19/177

    CPC分类号： H03K19/17736 ,  H03K19/17704

    摘要： In a programmable gate array ("PGA"), logic cells therein are programmed to create a combined output with enhanced current driving ability. Specifically, a first logic cell is programmed to have a first output and a second logic cell is programmed to have a second output. The first and second outputs are connected within the PGA forming a combined output having enhanced current driving ability by the first logic cell and the second logic cell. The first and second logic cells are programmed with identical logic functions such that they operate in parallel.

    摘要翻译： 在可编程门阵列（“PGA”）中，其中的逻辑单元被编程以产生具有增强的电流驱动能力的组合输出。 特别地，第一逻辑单元被编程为具有第一输出，并且第二逻辑单元被编程为具有第二输出。 第一和第二输出端连接在PGA中，形成具有由第一逻辑单元和第二逻辑单元增强的电流驱动能力的组合输出。 第一和第二逻辑单元被编程为具有相同的逻辑功能，使得它们并行操作。