公开(公告)号：US20250065254A1

公开(公告)日：2025-02-27

申请号：US18944483

申请日：2024-11-12

Applicant: Taiwan Semiconductor Manufacturing Company, LTD.

Inventor： Jyh-Shiou Hsu ,  Wen-Hsun Tsai ,  Chien-Chun Hu ,  Kuang-Wei Cheng ,  Sung-Ju Huang

IPC: B01D46/10 ,  B01D29/01 ,  B01D35/30 ,  B01D39/20 ,  B01D61/18 ,  H01L21/673

Abstract: A method is provided for supporting environmental control in a semiconductor wafer processing space, the method includes: flowing a first gas under pressure in a first direction through a first diffuser tube, thereby generating a first lateral flow of gas through a sidewall of the first diffuser tube; flowing a second gas under pressure in a second direction through a second diffuser tube, thereby generating a second lateral flow of gas through a sidewall of the second diffuser tube, the second direction being opposite the first direction; combining the first and second lateral flows of gas within a housing; and outputting the combined lateral flows of gas from the housing to produce a laminar gas flow covering an opening to the semiconductor wafer processing space.

公开(公告)号：US12237197B2

公开(公告)日：2025-02-25

申请号：US18769250

申请日：2024-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Lien Linus Lu ,  Cormac Michael O'Connell

IPC: G06F21/00 ,  B25J9/16 ,  H01L21/67 ,  H01L21/673 ,  H01L21/68 ,  B25J11/00

Abstract: Disclosed is a physical unclonable function generator circuit and method. In one embodiment, a physical unclonable function (PUF) generator comprising: a plurality of PUF cells, wherein each of the plurality of PUF cells comprises a first MOS transistor and a second MOS transistor, wherein terminal S of the first MOS transistor is connected to terminal D of the second MOS transistor at a dynamic node, terminal D of the first MOS transistor is coupled to a first bus and terminal G of the first NMOS transistor is coupled to a second bus, and terminals S and G of the second NMOS transistor are coupled to ground; a plurality of dynamic flip-flop (DFF) circuits wherein each of the plurality of DFF circuits is coupled to each of the plurality of PUF cells respectively; a population count circuit coupled to the plurality of DFF circuits; and an evaluation logic circuit having an input coupled to the population count circuit and an output coupled to the plurality of DFF circuits.

公开(公告)号：US20250038025A1

公开(公告)日：2025-01-30

申请号：US18918311

申请日：2024-10-17

Applicant: GUDENG PRECISION INDUSTRIAL CO., LTD.

Inventor： Ming-Chien Chiu ,  Chia-Ho Chuang ,  Kuo-Hua Lee ,  Shu-Hung Lin ,  Hao-Kang Hsia

IPC: H01L21/673

Abstract: The present invention provides a wafer container and a gas diffusion device applied in the wafer container. The wafer container includes a shell, and all components included and applied on the shell are made of thermal resistance materials. The gas diffusion device and the wafer container, when assembled together, utilize a coupling structure and a collar as a protection mechanism for the gas diffusion device. The gas diffusion device has a buffering chamber that provides a buffering tolerance and a communicating space for the gas before the gas enters an interior space of the wafer container.

公开(公告)号：US20250038024A1

公开(公告)日：2025-01-30

申请号：US18814094

申请日：2024-08-23

Applicant: Applied Materials, Inc.

Inventor： Douglas Brian Baumgarten ,  Russell Kaplan ,  Amitabh Puri ,  Paul B. Reuter

IPC: H01L21/673 ,  C23C16/44 ,  C23C16/455 ,  C23C16/458 ,  C23C16/52 ,  C23C16/54 ,  H01L21/67 ,  H01L21/677

Abstract: Disclosed are implementations for efficient purging of substrate carriers (and content held therein) and preventing external contaminants from entering a gas purge apparatus by coupling the gas purge apparatus to a substrate carrier, performing a first gas purging session of an environment of the substrate carrier, receiving a first signal of a first signal type, responsive to receiving the first signal, keeping the gas purge apparatus coupled to the substrate carrier, performing a second gas purging session of the environment of the substrate carrier, receiving a second signal of a second signal type, and, responsive to receiving the second signal, decoupling the purge apparatus from the substrate carrier.

公开(公告)号：US12211731B2

公开(公告)日：2025-01-28

申请号：US17659107

申请日：2022-04-13

Applicant: DISCO CORPORATION

Inventor： Kazuma Sekiya

IPC: H01L21/683 ,  H01L21/67 ,  H01L21/673 ,  H01L21/677

Abstract: A wafer processing method includes a wafer accommodating step of accommodating a wafer in a vacuum chamber, a protective sheet disposing step of disposing a protective sheet on a front surface of the wafer, a decompression step of decompressing the inside of the vacuum chamber, after the wafer accommodating step and the protective sheet disposing step, a press-fitting step of pressing the protective sheet against a peripheral marginal area of the wafer in the vacuum chamber to press-fit the protective sheet to the peripheral marginal area, after the decompression step, and a conveying-out step of opening the vacuum chamber to atmosphere to bring the protective sheet into close contact with the front surface of the wafer by atmospheric pressure and conveying out the wafer, after the press-fitting step.

公开(公告)号：US20250029855A1

公开(公告)日：2025-01-23

申请号：US18355048

申请日：2023-07-19

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Michael J. SEDDON

IPC: H01L21/673 ,  B65D61/00

Abstract: Implementations of a substrate carrier may include a frame including an inner perimeter, the inner perimeter configured to be smaller than a perimeter of an organic substrate panel including multiple semiconductor die coupled thereto; and an outer perimeter configured to be larger than the perimeter of the organic substrate panel; wherein an edge of the frame between the inner perimeter and outer perimeter may be configured to rest against the organic substrate panel to prevent warpage during a heating operation.

公开(公告)号：US20250022702A1

公开(公告)日：2025-01-16

申请号：US18904931

申请日：2024-10-02

Applicant: Kokusai Electric Corporation

Inventor： Masayuki ASAI ,  Tomoki IMAMURA ,  Kazuyuki OKUDA ,  Yasuhiro INOKUCHI ,  Norikazu MIZUNO

IPC: H01L21/02 ,  C23C16/458 ,  C23C16/50 ,  C23C16/52 ,  H01L21/673

Abstract: Provided is a method of processing a substrate including: forming a film on the substrate by performing a cycle, multiple times, including non-simultaneously performing: (a) supplying a precursor gas and inert gas to the substrate; and (b) supplying a reaction gas to the substrate. In (a), at least one of the precursor and inert gas stored in first tank is supplied to the substrate, and at least one of the precursor and inert gas stored in second tank is supplied to the substrate. A concentration or amount of the precursor gas differs between the first and second tank. Further, in (a), the process chamber is filled with the inert gas before the precursor gas and the inert gas are supplied to the substrate.

公开(公告)号：US12198958B2

公开(公告)日：2025-01-14

申请号：US17386851

申请日：2021-07-28

Applicant: GUDENG PRECISION INDUSTRIAL CO., LTD.

Inventor： Ming-Chien Chiu ,  Chia-Ho Chuang ,  Hsin-Min Hsueh ,  Yun-Zi Lin

IPC: H01L21/673 ,  G03F7/00 ,  G08C17/02 ,  H05K5/00 ,  H05K5/02

Abstract: The invention discloses a substrate storage apparatus having a detecting device detachably connecting to an outer pod. The detecting device includes a sensing member having a sensing terminal, a cavity and a sensor. The sensing terminal detachably connects to the outer pod such that the sensing terminal exposes in an accommodating space inside of the outer pod. The cavity receiving the sensor extends to an outside of the outer pod and the accommodating space. The cavity communicates with the accommodating space through the sensing terminal, allowing the sensor to read information regarding the accommodating space.

公开(公告)号：US12193164B2

公开(公告)日：2025-01-07

申请号：US18338679

申请日：2023-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shen-Min Yang ,  Pu Kuan Fang ,  Jyh-Shiou Hsu ,  Mu-Tsang Lin

IPC: H05K3/00 ,  H01L21/673

Abstract: The present disclosure describes a storage device including a top panel, a bottom panel, a back panel, a front panel, and two side panels configured to form an enclosed volume. The storage device further includes multiple slots disposed at inner surfaces of the two side panels and configured to hold a substrate, a gas diffuser disposed at an inner surface of the back panel and configured to provide a purge gas to the enclosed volume, an isolation gas device disposed on an inner surface of the top panel and adjacent to a top portion of the front panel, and an isolation gas line configured to connect the isolation gas device to the gas diffuser. The isolation gas device is configured to inject the purge gas into a front portion of the storage device and in a direction from the top panel toward the bottom panel.

公开(公告)号：US12189311B2

公开(公告)日：2025-01-07

申请号：US18316574

申请日：2023-05-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Hsun Chen ,  Yi-Zhen Chen ,  Jhan-Hong Yeh ,  Han-Lung Chang ,  Tzung-Chi Fu ,  Li-Jui Chen

IPC: G03F7/00 ,  H01L21/673 ,  H01L21/683 ,  H01L21/687

Abstract: A reticle carrier described herein is configured to quickly discharge the residual charge on a reticle so as to reduce, minimize, and/or prevent particles in the reticle carrier from being attracted to and/or transferred to the reticle. In particular, the reticle carrier may be configured to provide reduced capacitance between an inner baseplate of the reticle carrier and the reticle. The reduction in capacitance may reduce the resistance-capacitance (RC) time constant for discharging the residual charge on the reticle, which may increase the discharge speed for discharging the residual charge through support pins of the reticle carrier. The increase in discharge speed may reduce the likelihood that an electrostatic force in the reticle carrier may attract particles in the reticle carrier to the reticle. This may reduce pattern defects transferred to substrates that are patterned using the reticle, may increase semiconductor device manufacturing quality and yield, and may reduce scrap and rework of semiconductor devices and/or wafers.