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公开(公告)号：US20230369277A1
公开(公告)日：2023-11-16
申请号：US18357644
申请日：2023-07-24
发明人： Michael J. SEDDON , Chee Hiong CHEW
IPC分类号： H01L23/00 , H01L21/78 , H01L23/482 , H01L21/683
CPC分类号： H01L24/32 , H01L24/11 , H01L21/78 , H01L23/482 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/27 , H01L24/29 , H01L21/6836 , H01L24/83 , H01L24/94 , H01L24/28 , H01L24/30 , H01L24/31 , H01L24/33 , H01L2224/13166 , H01L2224/13155 , H01L2224/13147 , H01L2224/13139 , H01L2224/13111 , H01L2924/01327 , H01L2224/11849 , H01L2224/1308 , H01L2224/8481 , H01L2224/8581 , H01L2224/8681 , H01L21/4825
摘要： Implementations of a semiconductor package may include a pin coupled to a substrate. The pin may include a titanium sublayer, a nickel sublayer, and one of a silver and tin intermetallic layer or a copper and tin intermetallic layer, the one of the silver and tin intermetallic layer or the copper and tin intermetallic layer having a melting temperature greater than 260 degrees Celsius. The one of the silver and tin intermetallic layer or the copper and tin intermetallic layer may be formed by reflowing a tin layer and one of a silver layer or copper layer with a silver layer of the substrate where the substrate may be directly coupled to the one of the silver and tin intermetallic layer or the copper and tin intermetallic layer. The substrate may include a copper layer that was directly coupled with the silver layer before the reflow.
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公开(公告)号：US20230028096A1
公开(公告)日：2023-01-26
申请号：US17937499
申请日：2022-10-03
发明人： Michael J. SEDDON
IPC分类号： H01L21/768 , H01L21/3213 , H01L21/78
摘要： Implementations of die singulation systems and related methods may include forming a plurality of die on a first side of a substrate, forming a seed layer on a second side of a substrate opposite the first side of the substrate, using a shadow mask, applying a mask layer over the seed layer, forming a backside metal layer over the seed layer, removing the mask layer, and singulating the plurality of die included in the substrate through removing substrate material in the die street and through removing seed layer material in the die street.
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公开(公告)号：US20220367305A1
公开(公告)日：2022-11-17
申请号：US17816450
申请日：2022-08-01
IPC分类号： H01L23/31 , H01L23/528 , H01L23/60 , H01L23/00
摘要： Implementations of a semiconductor device may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be formed by at least two semiconductor die. The warpage of one of the first largest planar surface or the second largest planar surface may be less than 200 microns.
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公开(公告)号：US20220238342A1
公开(公告)日：2022-07-28
申请号：US17659068
申请日：2022-04-13
摘要： Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; stress relief etching the second side of the semiconductor substrate; applying a backmetal over the second side of the semiconductor substrate; removing one or more portions of the backmetal through jet ablating the second side of the semiconductor substrate; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.
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公开(公告)号：US20220165622A1
公开(公告)日：2022-05-26
申请号：US17104302
申请日：2020-11-25
发明人： Michael J. SEDDON
IPC分类号： H01L21/78
摘要： Implementations of a semiconductor substrate singulation process may include applying a fluid jet to a material of a die street of a plurality of die streets included in a semiconductor substrate where the semiconductor substrate may include: a plurality of die separated by the plurality of die streets; and a plurality of die support structures coupled thereto; and singulating the plurality of die and the plurality of die support structures at the plurality of die streets using the fluid jet. The fluid jet may be moved only along a length of the die street.
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公开(公告)号：US20210343604A1
公开(公告)日：2021-11-04
申请号：US17305624
申请日：2021-07-12
发明人： Michael J. SEDDON
IPC分类号： H01L21/66 , H01L23/00 , H01L21/263
摘要： Implementations of a method for healing a crack in a semiconductor substrate may include identifying a crack in a semiconductor substrate and heating an area of the semiconductor substrate including the crack until the crack is healed.
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公开(公告)号：US20200243366A1
公开(公告)日：2020-07-30
申请号：US16505949
申请日：2019-07-09
发明人： Michael J. SEDDON , Takashi NOMA
IPC分类号： H01L21/68 , H01L21/78 , H01L23/544
摘要： Implementations of a method of making a plurality of alignment marks on a wafer may include: providing a wafer including an alignment feature on a first side of the wafer. The method may include aligning the wafer using a camera focused on the first side of the wafer. The wafer may be aligned using the alignment feature on the first side of the die. The wafer may also include creating a plurality of alignment marks on a second side of the wafer through lasering, sawing, or scribing.
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公开(公告)号：US20200185334A1
公开(公告)日：2020-06-11
申请号：US16791879
申请日：2020-02-14
发明人： Michael J. SEDDON
IPC分类号： H01L23/544 , H01L21/02 , H01L23/00 , H01L21/78 , H01L21/304 , H01L21/683
摘要： A semiconductor wafer has a base material with a first thickness and first and second surfaces. A wafer scribe mark is disposed on the first surface of the base material. A portion of an interior region of the second surface of the base material is removed to a second thickness less than the first thickness, while leaving an edge support ring of the base material of the first thickness and an asymmetric width around the semiconductor wafer. The second thickness of the base material is less than 75 micrometers. The wafer scribe mark is disposed within the edge support ring. The removed portion of the interior region of the second surface of the base material is vertically offset from the wafer scribe mark. A width of the edge support ring is wider to encompass the wafer scribe mark and narrower elsewhere around the semiconductor wafer.
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公开(公告)号：US20200051878A1
公开(公告)日：2020-02-13
申请号：US16656182
申请日：2019-10-17
发明人： Michael J. SEDDON
IPC分类号： H01L21/66 , H01L21/683 , G01R31/28 , H01L21/78
摘要： Implementations of methods of making a semiconductor device may include: providing a partial semiconductor wafer. The method may also include providing a wafer holder including a tape portion with one or more openings through the tape portion. The method may include mounting the partial semiconductor wafer over the one or more openings in the tape portion of the wafer holder and providing an electrical connection to the partial semiconductor wafer through the one or more openings in the tape portion during probe test.
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公开(公告)号：US20190006169A1
公开(公告)日：2019-01-03
申请号：US16126717
申请日：2018-09-10
发明人： Michael J. SEDDON
IPC分类号： H01L21/02 , H01L21/67 , H01L23/544 , H01L21/66 , H01L21/78 , H01L21/768 , B24B7/22 , H01L21/304 , B24B55/06
摘要： A semiconductor wafer has a base material. The semiconductor wafer may have an edge support ring. A grinding phase of a surface of the semiconductor wafer removes a portion of the base material. The grinder is removed from or lifted off the surface of the semiconductor wafer during a separation phase. The surface of the semiconductor wafer and under the grinder is rinsed during the grinding phase and separation phase to remove particles. A rinsing solution is dispensed from a rinsing solution source to rinse the surface of the semiconductor wafer. The rinsing solution source can move in position while dispensing the rinsing solution to rinse the surface of the semiconductor wafer. The grinding phase and separation phase are repeated during the entire grinding operation, when grinding conductive TSVs, or during the final grinding stages, until the final thickness of the semiconductor wafer is achieved.
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