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公开(公告)号：US20230136596A1
公开(公告)日：2023-05-04
申请号：US18047106
申请日：2022-10-17
发明人： David Vincenzoni
摘要： A clock recovery circuit comprises an input node receiving a data signal having a data rate, and a digital oscillator producing a local clock signal with a frequency higher than the data rate. A counter clocked by the local clock signal has its count value sampled and reset at the rising and falling edges of the data signal, and a storage block coupled to the counter stores a count value that is updated in response to the current sampled count value of the counter lying in an update range between lower and upper bounds. A threshold value set is produced as a function of the updated count value stored in the storage block. Sampling circuitry receives and samples the data signal, and provides a sampled version of the data signal in response to the count value of the counter reaching any of the threshold values.
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公开(公告)号：US11641267B2
公开(公告)日：2023-05-02
申请号：US17443792
申请日：2021-07-27
发明人： Jong Suk Lee , Young Bok Kim , Chung Hwan Son , Seok Jae Oh , Soo Yeun Lee , Yeh Ju Ka
摘要： The present disclosure discloses a clock and data recovery circuit. The clock and data recovery circuit may include a clock recovery unit configured to output a recovery clock signal by operating a first time-to-digital conversion circuit or a second time-to-digital conversion circuit depending on a phase difference between a clock of an input signal and the recovery clock signal, and a data recovery unit configured to sample data from the input signal and output recovery data.
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公开(公告)号：US20230122556A1
公开(公告)日：2023-04-20
申请号：US17935618
申请日：2022-09-27
申请人： Diodes Incorporated
发明人： Yu-Wei Lin , Yi Sheng Lin , Nanyuan Chen
摘要： Disclosed are some examples of Phase interpolator circuitry used in retimer systems. The phase interpolator circuitry includes a phase interpolator configured to: receive the phase control signal, generate, based on the phase control signal, an output clock signal, and provide the output clock signal to the transmitter to track a plurality data packets. Phase interpolator circuitry is coupled with clock data recovery circuitry. In some implementations, clock data recovery circuitry is coupled between a receiver and a transmitter. The clock data recovery circuitry is configured to: extract a data component from an input data signal associated with the receiver, provide the data component to the transmitter, and generate a phase control signal.
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公开(公告)号：US20230090431A1
公开(公告)日：2023-03-23
申请号：US17810845
申请日：2022-07-06
申请人： Intel Corporation
发明人： Elan BANIN , Eytan MANN , Rotem BANIN , Ronen GERNIZKY , Ofir DEGANI , Igal KUSHNIR , Shahar PORAT , Amir RUBIN , Vladimir VOLOKITIN , Elinor KASHANI , Dmitry FELSENSTEIN , Ayal ESHKOLI , Tal DAVIDSON , Eng Hun OOI , Yossi TSFATI , Ran SHIMON
摘要： An apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.
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公开(公告)号：US11606186B2
公开(公告)日：2023-03-14
申请号：US17684273
申请日：2022-03-01
申请人： Kandou Labs, S.A.
发明人： Armin Tajalli
摘要： Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.
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公开(公告)号：US11601156B2
公开(公告)日：2023-03-07
申请号：US17353351
申请日：2021-06-21
申请人： MediaTek Inc.
发明人： Yu-Hsien Chang , Po-Chun Huang , Pi-An Wu , Wen-Hsien Chiu , Tzu-Wen Sung
摘要： Disclosed herein are devices and methods to reduce unwanted CIM3 emission in a wireless communication device, such that the transmit (TX) power level applied in a RU can be increased without exceeding a regulatory emission requirement. In some aspects, unwanted emission may be reduced by shifting or changing local oscillator (LO) frequencies during TX operation. Some embodiments are directed to a fast-locking PLL with adjustable bandwidth that can be controlled to increase the PLL bandwidth during the RX to TX transition to provide a fast locking to a new LO frequency. Some aspects are directed to configuring an LO frequency shift amount for different RUs when multiple RUs are allocated within a frequency band.
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公开(公告)号：US11575498B2
公开(公告)日：2023-02-07
申请号：US17353845
申请日：2021-06-22
发明人： Meng-Chih Weng
摘要： A clock and data recovery circuit includes a voltage controlled oscillator, a frequency detector and a control circuit. The voltage controlled oscillator is configured to generate a clock signal according to a voltage signal. The frequency detector is configured to detect whether increasing a frequency of the clock signal is required according to a plurality of sampling results of the input data signal and accordingly generate a first up control signal. The control circuit is coupled to the voltage controlled oscillator and the frequency detector and configured to adjust the voltage signal according to the first up control signal. The clock and data recovery circuit operates in a data recovery mode after detecting that the frequency of the clock signal is locked, and the frequency detector is configured to detect whether increasing the frequency of the clock signal is required in the data recovery mode.
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公开(公告)号：US20230033295A1
公开(公告)日：2023-02-02
申请号：US17788709
申请日：2021-01-05
申请人： FANUC CORPORATION
发明人： Takurou HAYASHI
IPC分类号： H04L7/033
摘要： Provided are a communication device, an industrial machine, and a communication method that contribute to accurate evaluation of communication quality. The present invention comprises: a reception unit that receives a serial signal; and a signal string acquisition unit that samples the serial signal at second periods that are shorter than a first period, which is a 1-bit period of the serial signal, thereby acquiring a signal string corresponding to 1 bit of the serial signal.
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公开(公告)号：US20230006808A1
公开(公告)日：2023-01-05
申请号：US17854176
申请日：2022-06-30
发明人： Horst WEBER , Franz MEISL
摘要： A method for reception of a signal by a subscriber of a real-time network. The signal includes a signal clock having a signal clock frequency and the subscriber includes a counter, which has a counter clock with a counter clock frequency and which maps a local time of the subscriber. The method includes sampling the signal with a reception clock of a reception counter of the subscriber, the reception clock being derived from the counter clock, whereby the reception counter maps the local time of the subscriber, adapting a phase position of the reception clock to a phase position of the signal clock when said reception clock is derived from the counter clock, and sampling the signal at a reception clock frequency of the reception counter
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公开(公告)号：US11533117B2
公开(公告)日：2022-12-20
申请号：US17228647
申请日：2021-04-12
申请人： John W Bogdan
发明人： John W Bogdan
摘要： The Digital Time Processing over Time Sensitive Networks (DTP TSN) disclosed herein is contributing methods, systems and circuits for using a Precision Time Protocol (PTP) such as IEEE 1588 for distributing a master time secured by a master unit to slave units by utilizing slave clocks recovered from PTP messages and/or compatible with them data receiver clocks for maintaining a local slave time which is increased to a local master time by adding to it an estimate of a transmission delay derived by processing PTP messages, wherein such distribution of the master time includes filtering out phase noise of a timing referencing signals communicated by PTP messages in order to produce accurate timing implementing signals such as the slave clock, local slave time and local master time.
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