公开(公告)号：US20250047288A1

公开(公告)日：2025-02-06

申请号：US18710693

申请日：2022-09-29

Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION

Inventor： SATOSHI FUKUDA ,  TOMOHIRO MATSUMOTO

IPC: H03L7/08 ,  H04B1/04 ,  H04L7/033

Abstract: In a system that transmits and receives data, the correction of the frequency of a clock signal is less frequently performed. A clock signal generation unit generates a transmission clock signal. A transmission unit transmits the transmission clock signal. An error acquisition unit acquires an external measurement error that is an error in a frequency of a reception clock signal measured by a reception device that receives the transmission clock signal and generates the reception clock signal from the transmission clock signal. A frequency control unit controls a frequency of the transmission clock signal based on the external measurement error and a measurement value measured on a transmission side.

公开(公告)号：US12218786B1

公开(公告)日：2025-02-04

申请号：US17991747

申请日：2022-11-21

Applicant: Cadence Design Systems, Inc.

Inventor： Hemlata Bist ,  Rohit Mishra ,  Harshit Jaiswal ,  Shubham Agarwal

IPC: H04L25/49 ,  H04B14/02 ,  H04L7/00 ,  H04L7/033

Abstract: A technical solution is directed to a clock recovery apparatus for multi-level signaling on a single-lane communication interface. The apparatus can use bin-map logic to successfully recover a common clock per symbol received on the multi-level signal interface. The multi-level signal can be PAM4 signaling where two bits are encoded to represent four levels. The clock recovery apparatus can detect signal level through individual edge detectors for each of the two bits and can handle jitter up to half-clock period.

公开(公告)号：US20250030534A1

公开(公告)日：2025-01-23

申请号：US18354075

申请日：2023-07-18

Applicant: Ciena Corporation

Inventor： Kenneth Edward Neudorf

IPC: H04L7/033 ,  G06F1/08

Abstract: An apparatus includes circuitry configured to receive a fill level from N first-in, first-out (FIFOs), N is an integer that is greater than or equal to 1, determine a module clock speed based on the fill level, and program a phase lock loop (PLL) based on the determined module clock speed where the PLL provides a module clock at the module clock speed to a packet processing circuit configured to receive packets from the N FIFOs. A packet processing module includes N FIFOs. N is an integer that is greater than or equal to 1; a programming state machine configured to receive a fill level from the N FIFOs and to program a PLL based thereon; and a packet processing circuit configured to receive packets from the N FIFOs, wherein the packet processing circuit receives a module clock from the PLL with a speed determined by the programming state machine.

公开(公告)号：US12200096B2

公开(公告)日：2025-01-14

申请号：US18237375

申请日：2023-08-23

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe

IPC: H04L7/033 ,  H04L7/00

Abstract: An integrated circuit receiver is disclosed comprising a data receiving circuit responsive to a timing signal to detect a data signal and an edge receiving circuit responsive to the timing signal to detect a transition of the data signal. One of the data or edge receiving circuits comprises an integrating receiver circuit while the other of the data or edge sampling circuits comprises a sampling receiver circuit.

公开(公告)号：US20240430071A1

公开(公告)日：2024-12-26

申请号：US18340787

申请日：2023-06-23

Applicant: QUALCOMM Incorporated

Inventor： Faramarz Sabouri ,  Ahmed Abbas Mohamed Helmy ,  Mehran Bakhshiani ,  Bindu Gupta

IPC: H04L7/033 ,  H04L27/26

Abstract: This disclosure provides systems, methods, and devices for wireless communications that support enhanced phase calibration operations. In a first aspect, an apparatus for wireless communications includes a processing system. The processing system is configured to cause the wireless communication device to: receive a reference signal at a respective input of a plurality of receive chains; process, by each receive chain, the reference signal to generate a respective output signal; determine, for each receive chain, a phase alignment difference between the respective output signal of the receive chain and a reference output signal of a reference receive chain of the plurality of receive chains; and adjust a phase alignment of a divider of at least one receive chain of the plurality of receive chains based on the determined phase alignment difference for the at least one receive chain. Other aspects and features are also claimed and described.

公开(公告)号：US12166583B2

公开(公告)日：2024-12-10

申请号：US16691135

申请日：2019-11-21

Applicant: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V. ,  Diehl Metering GmbH

Inventor： Gerd Kilian ,  Josef Bernhard ,  Thomas Kauppert ,  Hristo Petkov ,  Johannes Wechsler ,  Jakob Kneissl ,  Raphael Mzyk ,  Klaus Gottschalk ,  Dominik Soller ,  Michael Schlicht

IPC: H04L1/00 ,  H04L7/033 ,  H04L27/20 ,  H04W12/03

Abstract: The innovation relates to technologies by which the signal characteristics and, hence, environmental conditions of a transmitter can be concealed. In one aspect, a data transmitter comprises a transmitter and a changer, wherein the transmitter is configured to transmit a signal, wherein at least one signal parameter of the signal depends on at least one environmental parameter in an environment of the data transmitter, wherein the changer is configured to change the at least one signal parameter of the signal or a parameter on which the at least one signal parameter of the signal depends, in order to conceal the at least one environmental parameter.

公开(公告)号：US20240364493A1

公开(公告)日：2024-10-31

申请号：US18141189

申请日：2023-04-28

Applicant: Analog Devices, Inc.

Inventor： Narendra M.K. Rao ,  Rajasekhar Nagulapalli

IPC: H04L7/00 ,  H04L7/033

CPC classification number: H04L7/0025 ,  H04L7/0087 ,  H04L7/0337

Abstract: A phase interpolator for generating a phase interpolated output signal between two phase separated input signals received at two phase separated input signal nodes may include a plurality of circuit elements. The plurality of circuit elements may include at least one of resistors or capacitors, in a series arrangement between the two phase separated input signal nodes, where respective connection points between respective ones of the plurality of circuit elements may provide at least one intermediate phase interpolated signal. The phase interpolator may also include selection circuitry, which may be configured to select the phase interpolated output signal from the at least one intermediate phase interpolated signal.

公开(公告)号：US20240348420A1

公开(公告)日：2024-10-17

申请号：US18647834

申请日：2024-04-26

Applicant: Maxim Integrated Products, Inc.

Inventor： Jerzy A. Teterwak

IPC: H04L7/033 ,  H03L7/08 ,  H03L7/087 ,  H04L7/00

CPC classification number: H04L7/033 ,  H03L7/0807 ,  H03L7/087 ,  H04L7/0004

Abstract: A clock recovery circuit includes a clock detector configured to receive a serial data stream from a remote device over a reverse channel, wherein the serial data stream includes clock reference data, reverse channel data, or a combination of the clock reference data and the reverse channel data, and the clock detector configured to output a clock detect signal in response to detecting the clock reference data in the serial data stream; a phase lock loop including a first detector configured to receive the serial data stream and to detect phase and frequency; and a controller configured to receive the clock detect signal and to selectively enable the first detector based on the clock detect signal.

公开(公告)号：US12120210B2

公开(公告)日：2024-10-15

申请号：US17993776

申请日：2022-11-23

Applicant: Marvell Asia Pte Ltd

Inventor： Basel Alnabulsi ,  Yu Liao ,  Benjamin Smith ,  Jamal Riani

IPC: H04L7/00 ,  H04L7/033

CPC classification number: H04L7/0012 ,  H04L7/033

Abstract: An input signal is sampled at a current sampling phase by a sampler device of a receiver device. The sampled input signal is equalized by an adaptive equalizer of the receiver device. One or more parameters of the adaptive equalizer are adapted, based on the equalized input signal, under one or more adaptation constraints. Phase gradient information indicative of an offset of the current sampling phase from an optimal sampling phase is determined, and the one or more adaptation constraints of the adaptive equalizer are updated based on the phase gradient information to move the current sampling phase towards the optimal sampling phase.

公开(公告)号：US20240322994A1

公开(公告)日：2024-09-26

申请号：US18481226

申请日：2023-10-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Michael Chung WANG ,  Neal HAYS ,  Amir AMIRKHANY

IPC: H04L7/033 ,  H03L7/08 ,  H03L7/099

CPC classification number: H04L7/033 ,  H03L7/0807 ,  H03L7/099

Abstract: A system and method of clock and data recovery. In some embodiments, the method includes: setting a bias signal source to a first bias value, the bias signal source being connected to an input of a voltage-controlled oscillator of a clock and data recovery circuit; determining that a locked signal of a frequency feedback signal source equals a first feedback value; setting the bias signal source to a second bias value, different from the first bias value; determining that a locked signal of the frequency feedback signal source equals a second feedback value; determining that the second feedback value meets a termination criterion; and setting an operating value of the bias signal source to the second bias value.