Blockchain enabled crowdsourcing
    5.
    发明授权

    公开(公告)号:US11574268B2

    公开(公告)日:2023-02-07

    申请号:US15789635

    申请日:2017-10-20

    摘要: A method, computer system, and a computer program product for blockchain enabled crowdsourcing is provided. The present invention may include receiving an asset from a content provider. The present invention may also include deploying a smart contract based on the received asset, wherein the deployed smart contract includes a plurality of compensation rules. The present invention then may include partitioning the received asset into a plurality of fragments based on the deployed smart contract. The present invention may further include releasing the partitioned plurality of fragments into a blockchain network. The present invention may also include tracking each fragment within the released plurality of fragments using the smart contract.

    METHODS AND APPARATUS TO IMPROVE PERFORMANCE OF ENCRYPTION AND DECRYPTION TASKS

    公开(公告)号:US20230004358A1

    公开(公告)日:2023-01-05

    申请号:US17942995

    申请日:2022-09-12

    申请人: Intel Corporation

    IPC分类号: G06F7/72 H04L9/30 H04L9/34

    摘要: Methods, apparatus, systems, and articles of manufacture are disclosed. An example apparatus includes: interface circuitry to receive a first value and a second value; selector circuitry to select a first subset of bits and a second subset of bits from the first value; multiplier circuitry to: multiply the first subset to the second value during a first compute cycle; and multiply the second subset to the second value during a second compute cycle; left shift circuitry to perform a bitwise shift with a product of the first subset and the second value during the second compute cycle; adder circuitry to add a product of the second subset and the second value to a result of the plurality of bitwise shift operations during the second compute cycle; and comparator circuitry to determine the result of the modular multiplication based on a result of the addition during the second compute cycle.

    USER STATION FOR A SERIAL BUS SYSTEM, AND METHOD FOR COMMUNICATING IN A SERIAL BUS SYSTEM

    公开(公告)号:US20220407619A1

    公开(公告)日:2022-12-22

    申请号:US17777369

    申请日:2020-12-01

    申请人: Robert Bosch GmbH

    IPC分类号: H04L1/00 H04L9/34 H03M13/09

    摘要: A user station for a serial bus system. The user station includes a communication control device for controlling a communication of the user station with at least one other user station, and a transceiver device to serially transmit a transmission signal generated by the communication control device onto a bus and to serially receive signals from the bus. The communication control device generates the transmission signal according to a frame, and inserts a header check sum into the frame, only bits of a frame header that is situated in front of a data field provided for useful data in the frame being included in the computation. For computing the header check sum, the communication control device uses a predetermined starting value and a predetermined check sum polynomial.

    Smart compressor based on adaptive CPU/QAT scheduling method

    公开(公告)号:US11431480B2

    公开(公告)日:2022-08-30

    申请号:US16509307

    申请日:2019-07-11

    摘要: A method, apparatus, and system for assigning the execution of a cryptography and/or compression operation on a data segment to either a central processing unit (CPU) or a hardware cryptography/compression accelerator is disclosed. In particular, a data segment on which a cryptography and/or compression operation is to be executed is received. Status information relating to a CPU and a hardware cryptography/compression accelerator is determined. Whether the operation is to be executed on the CPU or on the hardware accelerator is determined based at least in part on the status information. In response to determining that the operation is to be executed on the CPU, the data segment is forwarded to the CPU for execution of the operation. On the other hand, in response to determining that the operation is to be executed on the hardware accelerator, the data segment is forwarded to the hardware accelerator for execution of the operation.

    Circuit concealing apparatus, calculation apparatus, and program

    公开(公告)号:US11095429B2

    公开(公告)日:2021-08-17

    申请号:US16348417

    申请日:2017-11-09

    IPC分类号: H04L9/06 G06F21/72 H04L9/34

    摘要: At least any one of input keys KA0, KA1, KB′0, and KB′1 is set so that the input keys KA0, KA1, KB′0, and KB′1 which satisfy KA1−KA0=KB′1−KB′0=di are obtained, and an output key Kig(I(A), I(B)) corresponding to an output value gi(I(A), I(B)) is set by using the input keys KA0, KA1, KB′0, and KB′1, where input values of a gate that performs a logical operation are I(A), I(B)∈{0, 1}, an output value of the gate is gi(I(A), I(B))∈{0, 1}, an input key corresponding to the input value I(A) is KAI(A), and an input key corresponding to the input value I(B) is KB′I(B).