公开(公告)号：WO2017099736A1

公开(公告)日：2017-06-15

申请号：PCT/US2015/064620

申请日：2015-12-09

Applicant: INTEL CORPORATION

Inventor： TELANG, Adwait ,  MUIRHEAD, John-Gerard ,  LEE, Kevin J. ,  PATTABHIRAMAN, Sriram ,  JEONG, James

IPC: H01L21/768

CPC classification number: H01L24/00 ,  H01L21/76837 ,  H01L23/145 ,  H01L23/147 ,  H01L23/49894 ,  H01L23/525 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/5385 ,  H01L2224/16225

Abstract: Embodiment of the present disclosure are directed to methods for forming an LMI landing pad on a silicon wafer. The method includes forming, on a substrate, a redistribution layer (RDL); forming, on the RDL and the substrate, a passivation layer covering the substrate and the RDL; forming, on the passivation layer, a patternable dielectric material layer; processing the patternable dielectric material layer to expose a portion of the passivation layer covering the RDL; processing the portion of the passivation layer covering the RDL to expose a portion of the RDL; and forming, on the exposed portion of the RDL, an LMI landing pad. The resulting wafer can include a redistribution line having a top portion and a sidewall portion; a passivation layer covering the sidewall portion; a dielectric layer covering the passivation layer; and a metal interface covering the top portion of the redistribution line.

Abstract translation: 本公开的实施例针对用于在硅晶片上形成LMI着陆焊盘的方法。 该方法包括在衬底上形成再分布层（RDL）; 在所述RDL和所述衬底上形成覆盖所述衬底和所述RDL的钝化层; 在钝化层上形成可图案化的电介质材料层; 处理可图案化的介电材料层以暴露覆盖RDL的部分钝化层; 处理覆盖RDL的部分钝化层以暴露部分RDL; 以及在RDL的暴露部分上形成LMI着陆垫。 所得晶片可包括具有顶部和侧壁部分的再分布线; 覆盖所述侧壁部分的钝化层; 覆盖钝化层的介电层; 和一个覆盖再分配线顶部的金属接口。

公开(公告)号：WO2018063324A1

公开(公告)日：2018-04-05

申请号：PCT/US2016/054778

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： SATTIRAJU, Seshu V. ,  GANESAN, Krishna Prakash ,  BHATIA, Ashish ,  SRIRAM, Vinay ,  MUIRHEAD, John ,  KOTHARI, Hiten ,  GUNAWAN, Aloysius A. ,  ARYASOMAYAJULA, Lavanya ,  GOWRISHANKAR, Shravan ,  PATTABHIRAMAN, Sriram ,  GUHA, Sudipto

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/48

Abstract: A stacked-chip assembly including a plurality of IC chips or die that are stacked, and electrically coupled by solder bonds. In accordance with some embodiments described further below, the solder bonds are to contact a back-side land that includes a diffusion barrier to reduce intermetallic formation and/or other solder-induced reliability issues. The back-side land may include an electrolytic nickel (Ni) barrier layer separating solder from a back-side redistribution layer trace. This electrolytic Ni may be of high purity, which at least in part, may enable the backside metallization stack to be of minimal thickness while still functioning as a diffusion barrier. In some embodiments, the back-side land composition and architecture is distinct from a front-side land composition and/or architecture.

Abstract translation: 包括堆叠的多个IC芯片或管芯并通过焊接电连接的堆叠芯片组件。 根据下面进一步描述的一些实施例，焊料接合将接触包括扩散阻挡层的背侧焊盘以减少金属间形成和/或其他焊料引起的可靠性问题。 背侧焊盘可以包括电解镍（Ni）阻挡层，从背侧再分配层迹线分离焊料。 该电解Ni可以具有高纯度，其至少部分地可以使得背面金属化叠层具有最小的厚度，同时仍然用作扩散阻挡层。 在一些实施例中，背面土地组合物和体系结构不同于正面土地组成和/或体系结构。