公开(公告)号：WO2008070812A2

公开(公告)日：2008-06-12

申请号：PCT/US2007/086702

申请日：2007-12-06

Applicant: FLYNN, David ,  THATCHER, Jonathan ,  ZAPPE, Michael ,  ATKISSON, David

Inventor： FLYNN, David ,  THATCHER, Jonathan ,  ZAPPE, Michael ,  ATKISSON, David

IPC: G06F3/06 ,  G06F11/10

CPC classification number: G06F12/121 ,  G06F1/183 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0613 ,  G06F3/0619 ,  G06F3/0643 ,  G06F3/065 ,  G06F3/0652 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0685 ,  G06F3/0688 ,  G06F9/52 ,  G06F9/54 ,  G06F11/108 ,  G06F12/0246 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/12 ,  G06F12/123 ,  G06F13/28 ,  G06F13/4022 ,  G06F13/426 ,  G06F2211/002 ,  G06F2211/103 ,  G06F2212/1044 ,  G06F2212/2022 ,  G06F2212/222 ,  G06F2212/69 ,  G06F2212/70 ,  G06F2212/7205 ,  H04L67/02 ,  H04L67/1097 ,  H05K7/1444 ,  H05K7/1487 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: An invention is disclosed for data storage with progressive RAID. A storage request receiver module (1702) receives a request to store data. A striping module (1704) calculates a stripe pattern for the data and each stripe includes N data segments. The striping module (1704) writes the N data segments to N storage devices (150). Each data segment is written to a separate storage device (150) within a set of storage devices (1604) assigned to the stripe. A parity-mirror module (1706) writes a set of N data segments to one or more parity-mirror storage devices (1602) within the set of storage devices. A parity progression module (1708) calculates a parity data segment on each parity-mirror device (1602) in response to a storage consolidation operation, and stores the parity data segments. The storage consolidation operation is conducted to recover storage space and/or data on a parity-mirror storage device (1602).

Abstract translation: 公开了一种用于具有渐进式RAID的数据存储的发明。 存储请求接收器模块（1702）接收存储数据的请求。 条带化模块（1704）计算数据的条纹图案，并且每个条带包括N个数据段。 条带模块（1704）将N个数据段写入N个存储装置（150）。 每个数据段被写入分配给条带的一组存储设备（1604）内的单独的存储设备（150）。 奇偶校验镜模块（1706）将一组N个数据段写入一组存储设备内的一个或多个奇偶校验镜像存储设备（1602）。 奇偶校验进行模块（1708）响应于存储合并操作计算每个奇偶校验镜设备（1602）上的奇偶校验数据段，并存储奇偶校验数据段。 进行存储整合操作以恢复奇偶校验镜存储设备（1602）上的存储空间和/或数据。

公开(公告)号：WO2007137141A3

公开(公告)日：2008-02-28

申请号：PCT/US2007069188

申请日：2007-05-17

Applicant: QUALCOMM INC ,  AHMED MUHAMMAD

Inventor： AHMED MUHAMMAD

IPC: G06F12/12 ,  G06F12/08

CPC classification number: G06F12/123 ,  G06F12/0859 ,  G06F12/126 ,  G06F12/128 ,  Y02D10/13

Abstract: Techniques for use in CDMA-based products and services, including replacing cache memory allocation so as to maximize residency of a plurality of set ways following a tag-miss allocation. Herein, steps forming a first-in, first-out (FIFO) replacement listing of victim ways for the cache memory, wherein the depth of the FIFO replacement listing approximately equals the number of ways in the cache set. The method and system place a victim way on the FIFO replacement listing only in the event that a tag-miss results in a tag-miss allocation, the victim way is placed at the tail of the FIFO replacement listing after any previously selected victim way. Use of a victim way on the FIFO replacement listing is prevented in the event of an incomplete prior allocation of the victim way by, for example, stalling a reuse request until such initial allocation of the victim way completes or replaying a reuse request until such initial allocation of the victim way completes.

Abstract translation: 在基于CDMA的产品和服务中使用的技术，包括替换高速缓存存储器分配，以便在标签错失分配之后最大化多个设置路径的驻留。 这里，形成用于高速缓冲存储器的受害方式的先入先出（FIFO）替换列表的步骤，其中FIFO替换列表的深度近似等于高速缓存集中的路数。 只有在标签错失导致标签错失分配的情况下，该方法和系统才会将受害者的方式置于FIFO替换列表中，受害者的方式将放置在先前选择的受害方式之后的FIFO替换列表的尾部。 在受害者方式的不完整的先前分配的情况下，通过停止重用请求直到受害方的初始分配完成或重放重用请求直到这样的初始化 受害方的分配完成。

公开(公告)号：WO2007002282A3

公开(公告)日：2007-09-20

申请号：PCT/US2006024291

申请日：2006-06-22

Applicant: INITIO SOFTWARE CORP AB ,  STANFILL CRAIG W

Inventor： STANFILL CRAIG W

IPC: G06F12/00 ,  G06F9/26 ,  G06F9/34 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F12/123

Abstract: A method, and corresponding software and system, is described for paging memory used for one or more sequentially-accessed data structure. The method includes providing a data structure (200) representing an order in which memory pages are to be reused; and maintaining the data structure according to a history of access to a memory page associated with one of the sequentially-accessed data structures. A position of the memory page in the order depends on a transition of sequential access off of the memory page.

Abstract translation: 描述了用于一个或多个顺序访问的数据结构的分页存储器的方法和相应的软件和系统。 该方法包括提供表示存储器页面将被重用的顺序的数据结构（200）; 以及根据对与顺序访问的数据结构之一相关联的存储器页面的访问历史来维护数据结构。 存储器页面中的顺序的位置取决于存储器页面的顺序访问的转换。

公开(公告)号：WO2007059215A2

公开(公告)日：2007-05-24

申请号：PCT/US2006044355

申请日：2006-11-15

Applicant: MIPS TECH INC ,  KNOTH MATTHIAS

Inventor： KNOTH MATTHIAS

IPC: G06F1/32 ,  G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0864 ,  G06F9/3802 ,  G06F12/123 ,  G06F2212/1028 ,  G06F2212/6082 ,  Y02D10/13

Abstract: Microprocessor having a power-saving instruction cache way predictor and instruction replacement scheme. In one embodiment, the processor includes a multi-way set associative cache, a way predictor, a policy counter, and a cache refill circuit. The policy counter provides a signal to the way predictor that determines whether the way predictor operates in a first mode or a second mode. Following a cache miss, the cache refill circuit selects a way of the cache and compares a layer number associated with a dataram field of the way to a way-set-layer number. The cache refill circuit writes a block of data to the field if the layer number is not equal to the way-set-layer number. If the layer number is equal to the way-set-layer number, the cache refill circuit repeats the above steps for additional ways until the block of memory is written to the cache.

Abstract translation: 具有省电指令高速缓存方式预测器和指令替换方案的微处理器。 在一个实施例中，处理器包括多路组相关高速缓存，方式预测器，策略计数器和高速缓存补充电路。 策略计数器向预测器提供一种信号，该方式确定预测器在第一模式或第二模式下的运行方式。 在缓存未命中之后，缓存补充电路选择高速缓存的方式，并将与方式的数据字段相关联的层号与方式集合号进行比较。 如果层号不等于路由集层号，高速缓存补充电路将一个数据块写入该字段。 如果层号等于路由集合号码，则缓存补充电路重复上述步骤以获得额外的方式，直到存储器块被写入高速缓存。

公开(公告)号：WO2007015955A2

公开(公告)日：2007-02-08

申请号：PCT/US2006028303

申请日：2006-07-21

Applicant: INVENSYS SYS INC ,  AVERGUN MIKHAIL ,  NARYZHNY YEVGENY V

Inventor： AVERGUN MIKHAIL ,  NARYZHNY YEVGENY V

IPC: G06F12/00

CPC classification number: G06F12/123

Abstract: Disclosed is a technique for managing items in a memory store. A "free-space size threshold" is set for the memory store. An age parameter is also set. When the amount of free space in the store decreases below the threshold, space in the store is freed up by removing memory items. Memory items older than specified by the age parameter are also removed. A "chain" of memory stores can be implemented. When a memory item is removed from the first store, it is added to the second store and so on. The techniques of the present invention can be implemented in each store in the chain, or the stores can use different memory management techniques.

Abstract translation: 公开了一种用于管理存储器存储器中的项目的技术。 为存储器存储设置“自由空间大小阈值”。 还设置一个年龄参数。 当商店中的可用空间量降低到阈值以下时，通过删除内存条目来释放商店中的空间。 由age参数指定的内存项目也会被删除。 可以实现存储器的“链”。 当从第一个商店中删除内存条目时，它将被添加到第二个商店，依此类推。 本发明的技术可以在链中的每个商店中实现，或者商店可以使用不同的存储器管理技术。

公开(公告)号：WO2004046933A1

公开(公告)日：2004-06-03

申请号：PCT/JP2002/012137

申请日：2002-11-20

Applicant: 富士通株式会社 ,  中尾 学

Inventor： 中尾 学

IPC: G06F12/12

CPC classification number: G06F12/123

Abstract: A memory controller comprising a single-port LRU RAM (26) holding replacement way information on replacement of a cache memory (a cache tag RAM (22) and a cache data RAM (23)), an LRU replacement way selecting section (27) for selecting a way to be replaced by an LRU algorithm depending on the replacement way information on the single-port LRU RAM (26), a random replacement way selecting section (105) for selecting a way to be replaced randomly without using the replacement way information, a hit decision section (102) for carrying out hit decision about first and second requests simultaneously made for an access to a cache memory by a CPU (10), and an arbiter section (104) for, if the hit decisions about the first and second requests are both cache misses, allowing the LRU replacement way selecting section (27) to select a way in response to the first request and allowing the random replacement way selecting section (105) to select a way in response to the second request.

Abstract translation: 一种存储器控制器，包括保存有关高速缓存存储器（高速缓存标签RAM（22）和高速缓冲存储器数据RAM（23））的更换的替换路信息的单端口LRU RAM（26），LRU替换路径选择部分（27） 用于根据单端口LRU RAM（26）上的替代方式信息来选择要由LRU算法代替的方式，随机替换方式选择部分（105），用于选择随机替换的方式，而不使用替换方式 信息，用于执行关于由CPU（10）访问高速缓冲存储器而同时进行的第一和第二请求的命中决定的命中决定部分（102），以及仲裁器部分（104），如果关于 第一和第二请求都是高速缓存未命中，允许LRU替换方式选择部分（27）响应于第一请求选择一种方式，并允许随机替换方式选择部分（105）响应于第二请求选择一种方式 。

公开(公告)号：WO0188720A3

公开(公告)日：2003-10-02

申请号：PCT/US0114088

申请日：2001-05-02

Applicant: SUPERSPEED SOFTWARE INC

Inventor： DEMPSEY MICHAEL ,  DICKMAN ERIC

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0866 ,  G06F12/0804 ,  G06F12/123 ,  G06F2212/311

Abstract: Methods of caching data in a computer wherein a cache is given a number of caching parameters. In a method for caching data in a computer having an operating system with a file caching mechanism, the file caching mechanism is selectively disabled and a direct block cache is accessed to satisfy a request of the request stream. Cache memory can be expanded by allocating memory to a memory table created in a user mode portion of the computer and having a set of virtual memory addresses. Methods of caching data can include creating an associative map, and optimizing the order of writes to a disk with a lazy writer. Methods are further assisted by displaying cache performance criteria on a user interface and allowing user adjustment of caching parameters such as cache size, cache block size and lazy writer aggressiveness. A user may further be given the ability to enable or disable a cache for a given selected disk volume.

Abstract translation: 在计算机中缓存数据的方法，其中缓存被给予多个缓存参数。 在具有具有文件缓存机制的操作系统的计算机中缓存数据的方法中，选择性地禁用文件缓存机制，并且访问直接块高速缓存以满足请求流的请求。 可以通过将内存分配给在计算机的用户模式部分中创建并具有一组虚拟存储器地址的存储器表来扩展缓存存储器。 缓存数据的方法可以包括创建关联映射，并且利用懒惰的作者来优化写入磁盘的顺序。 通过在用户界面上显示缓存性能标准并允许用户调整高速缓存参数（如高速缓存大小，缓存块大小和惰性写入器侵略性）来进一步协助方法。 还可以向用户赋予为给定的所选磁盘卷启用或禁用高速缓存的能力。

公开(公告)号：WO0057276A9

公开(公告)日：2002-06-27

申请号：PCT/US0008085

申请日：2000-03-24

Applicant: EXCELON CORP

Inventor： LEIVENT JONATHAN I

IPC: G06F12/00 ,  G06F12/08 ,  G06F12/10 ,  G06F12/12 ,  G06F17/30

CPC classification number: G06F17/30607 ,  G06F12/0866 ,  G06F12/1045 ,  G06F12/123

Abstract: For an object-oriented database system, an apparatus for virtual memory mapping and transaction management comprises at least one permanent storage and at least one database, at least one cache, and a processing unit including means, utilizing virtual addresses, to access data in the cache, means for mapping virtual to physical addresses, and means for retaining the cached data after a transaction. Data retained across transations will often not need further translation, referred to as forward relocation. Making cached data usable across a sequence of transactions often without requiring further translation, while working size of this data may be larger than a client computer's address space, is referred to as relocation optimization. The method uses a queue containing entities ordered by recency of use, and recycles address space of least-recently used bindings to preserve the validity of bindings necessary for the proper function of the client application with minimal overhead.

Abstract translation: 对于面向对象的数据库系统，用于虚拟存储器映射和事务处理的装置包括至少一个永久存储器和至少一个数据库，至少一个高速缓存和包括使用虚拟地址的装置来访问数据的装置 缓存，用于映射虚拟到物理地址的手段，以及用于在事务之后保留高速缓存的数据的装置。 通过跨过程保留的数据通常不需要进一步的翻译，称为向前迁移。 使缓存的数据在一系列事务中可用，通常不需要进一步的翻译，而该数据的工作大小可能大于客户端计算机的地址空间，被称为重定位优化。 该方法使用包含按照使用次序排序的实体的队列，并回收最近最少使用的绑定的地址空间，以最小的开销来保留客户端应用程序的正常功能所必需的绑定的有效性。

公开(公告)号：WO02039284A2

公开(公告)日：2002-05-16

申请号：PCT/US2001/045500

申请日：2001-11-02

IPC: G06F12/12 ,  G06F12/00

CPC classification number: G06F12/122 ,  G06F12/123

Abstract: Memory management systems and methods that may be employed, for example, to provide efficient management of memory for network systems. The disclosed systems and methods may utilize a multi-layer queue management structure to manage buffer/cache memory in an integrated fashion. The disclosed systems and methods may be implemented as part of an information management system, such as a network processing system that is operable to process information communicated via a network environment, and that may include a network processor operable to process network-communicated information and a memory management system operable to reference the information based upon a connection status associated with the content.

Abstract translation: 可用于例如为网络系统提供对存储器的有效管理的内存管理系统和方法。 所公开的系统和方法可以利用多层队列管理结构以集成的方式来管理缓冲器/高速缓冲存储器。 所公开的系统和方法可以被实现为信息管理系统的一部分，诸如可操作以处理经由网络环境传送的信息的网络处理系统，并且可以包括可操作以处理网络传送的信息的网络处理器和 存储器管理系统，其可操作以基于与所述内容相关联的连接状态来引用所述信息。

公开(公告)号：WO0152067A3

公开(公告)日：2002-03-07

申请号：PCT/US0100556

申请日：2001-01-04

Applicant: STORAGE TECHNOLOGY CORP

Inventor： VANDENBERGH HENK ,  MILILLO MICHAEL S ,  PETERSON GREGORY W

IPC: G06F12/12

CPC classification number: G06F12/123

Abstract: Each time a track is referenced, a value representing the last referenced age is entered for a track entry in a last referenced age table (LRAT). The last referenced age table is indexed by track. A second table, an age frequency table (AFT), counts all segments in use in each reference age. The AFT is indexed by the reference age of the tracks. When a track is referenced, the number of segments used for the track is added to a segment count associated with the last referenced age of the track. The segment count tallies the total number of segments in use for the reference age for all tracks referenced to that age. The number of segments used for the previous last referenced age of the track is subtracted from the segment count associated with the previous last referenced age in the AFT. When free space is needed, tracks are discarded from the LRAT by reference age, the oldest first. The range of ages to be discarded in the LRAT is calculated in the AFT by counting the total amount of segments used by each reference age until the total number of segments needed is realized. Counting is started at the AFT entry with the oldest reference age. The reference age of the last counted entry in the AFT is the discard age. The LRAT is scanned for reference ages between the old age and the discard age, and those reference ages are discarded.

Abstract translation: 每次轨道被引用时，都会为最后一次参考的年龄表（LRAT）中的轨道条目输入代表最后参考年龄的值。 最后参考的年龄表按轨道索引。 第二个表格，年龄频率表（AFT）计算每个参考年龄使用的所有细分。 AFT由轨道的参考年龄索引。 当轨道被引用时，用于轨道的段的数量被添加到与轨道的最后参考年龄相关联的段计数。 段计数与参考该年龄的所有轨道的参考年龄的总共段数一致。 用于前一次参考年龄的段的数量从与AFT中前一个参考年龄相关联的段计数中减去。 当需要可用空间时，轨道将从LRAT中被丢弃，参考年龄是最早的。 通过计算每个参考年龄段使用的段的总数，直到实现所需段的总数，在AFT中计算要在LRAT中舍弃的年龄范围。 计数开始于具有最早参考年龄的AFT条目。 AFT最后一次入场的参考年龄是丢弃年龄。 扫描LRAT在旧年龄和丢弃年龄之间参考年龄，并丢弃那些参考年龄。