公开(公告)号：WO2007143277A2

公开(公告)日：2007-12-13

申请号：PCT/US2007/066522

申请日：2007-04-12

Applicant: AWARE, INC. ,  TZANNES, Marcos, C.

Inventor： TZANNES, Marcos, C.

IPC: H04L12/56

CPC classification number: H04L45/72 ,  H03M13/00 ,  H03M13/09 ,  H03M13/091 ,  H03M13/2707 ,  H03M13/6513 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0057 ,  H04L1/08 ,  H04L1/1607 ,  H04L1/18 ,  H04L1/1809 ,  H04L1/1835 ,  H04L1/1874 ,  H04L12/5601 ,  H04L45/00 ,  H04L47/10 ,  H04L47/2433 ,  H04L47/2441 ,  H04L47/32 ,  H04L49/552 ,  H04L69/324 ,  H04L2012/5647

Abstract: Through the identification of different packet-types, packets can be handled based on an assigned packet handling identifier. This identifier can, for example, enable forwarding of latency-sensitive packets without delay and allow error-sensitive packets to be stored for possible retransmission. In another embodiment, and optionally in conjunction with retransmission protocols including a packet handling identifier, a memory used for retransmission of packets can be shared with other transceiver functionality such as, coding, decoding, interleaving, deinterleaving, error correction, and the like.

Abstract translation: 通过识别不同的分组类型，可以基于分配的分组处理标识符来处理分组。 例如，该标识符可以不延迟地转发等待时间敏感的分组，并且允许存储用于可能重传的错误敏感分组。 在另一实施例中，并且可选地与包括分组处理标识符的重传协议相结合，用于分组重传的存储器可以与诸如编码，解码，交织，去交织，纠错等的其他收发器功能共享。

公开(公告)号：WO2007103399A2

公开(公告)日：2007-09-13

申请号：PCT/US2007005737

申请日：2007-03-07

Applicant: APPLIED MATERIALS INC

Inventor： CHEN HUI ,  TULSHIBAGWALE SHESHRAJ L ,  TAKAHASHI HIDESHI ,  TOMITA TOSHIKAZU ,  FUJIKAWA TAKASHI

IPC: A46B7/10

CPC classification number: H04L1/0045 ,  H01L21/67046 ,  H03M13/09 ,  H03M13/3738 ,  H03M13/3776 ,  H03M13/41 ,  H04L1/0059 ,  H04L1/20 ,  H04L1/208

Abstract: System and methods for reducing false alarm in the presence of random signals are disclosed. Various embodiments are operable to receive via a data interface a data block having at least one frame, normalize soft bits of the data block and re-encode decoder output bits of the data block, calculate a normalized correlation metric from the normalized soft bits and re-encoded bits of the data block, compare the normalized correlation metric to a threshold, and reject the data block when the normalized correlation metric is below the threshold.

Abstract translation: 公开了用于在存在随机信号的情况下减少假警报的系统和方法。 各种实施例可操作以经由数据接口接收具有至少一个帧的数据块，对数据块的软比特进行归一化并重新编码数据块的解码器输出位，从归一化的软比特计算归一化的相关度量 数据块的编码比特，将归一化相关度量与阈值进行比较，并且当归一化相关度量低于阈值时，拒绝数据块。

公开(公告)号：WO2007052991A1

公开(公告)日：2007-05-10

申请号：PCT/KR2006/004643

申请日：2006-11-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KIM, Sang-Hyo ,  GU, Young-Mo ,  KWAK, Chang-Hyun

IPC: H03M13/09

CPC classification number: H03M13/29 ,  H03M13/09 ,  H03M13/2975

Abstract: An apparatus and method are provided for stopping iterative decoding in a channel decoder of a mobile communication system. Constituent decoding of received signals is performed and decoded signals are output. Hard decision processes for the decoded signals are performed and hard-decided signals are output. The hard-decided signals are cyclic redundancy check (CRC) encoded, and a determination is made as to whether the parities are identical and iterative decoding is stopped according to a determination result.

Abstract translation: 提供了一种用于在移动通信系统的信道解码器中停止迭代解码的装置和方法。 执行接收信号的组成解码并输出解码信号。 执行解码信号的硬判决处理，并输出硬决定信号。 硬判决信号是循环冗余校验（CRC）编码的，并且确定奇偶校验是否相同并且根据确定结果停止迭代解码。

公开(公告)号：WO2007034935A1

公开(公告)日：2007-03-29

申请号：PCT/JP2006/318899

申请日：2006-09-19

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD. ,  ITO, Masafumi ,  ATSUMI, Tomoaki

Inventor： ITO, Masafumi ,  ATSUMI, Tomoaki

IPC: H03M13/09 ,  G06K19/07

CPC classification number: H03M13/09 ,  H04B1/10

Abstract: An object of the present invention is to provide a CRC circuit with more simple structure and low power consumption. The CRC circuit includes a first shift register to a p-th shift register, a first EXOR to a (p-1)th EXOR, and a switching circuit. A data signal, a select signal, and an output of a last stage of the p-th shift register are inputted to the switching circuit, and the switching circuit switches a first signal or a second signal in response to the select signal to be outputted.

Abstract translation: 本发明的目的是提供一种具有更简单的结构和低功耗的CRC电路。 CRC电路包括到第p移位寄存器的第一移位寄存器，第一EXOR到第（p-1）个EXOR和开关电路。 数据信号，选择信号和第p移位寄存器的最后级的输出被输入到开关电路，并且开关电路响应于要输出的选择信号而切换第一信号或第二信号 。

公开(公告)号：WO2006125157A3

公开(公告)日：2007-03-29

申请号：PCT/US2006019456

申请日：2006-05-18

Applicant: TELEGENT SYSTEMS INC ,  GUO SHARORI

Inventor： GUO SHARORI

IPC: H03M13/15 ,  H03M13/09 ,  H04L1/00

CPC classification number: H03M13/09 ,  H04L1/0045 ,  H04L1/0057

Abstract: A first data packet is received within an integrated circuit device and stored within a first memory thereof starting at a first address that is determined by the size of one or more previously received data packets. An error descriptor value is updated within a second memory of the integrated circuit device, the error descriptor including an error field that indicates an error that is associated with the first data packet, an address field that indicates the first address within the first memory and a length field that indicates a range of storage locations to which the error applies. A multiple-bit error value is generated based, at least in part, on the error descriptor, each bit of the multiple-bit error value corresponding to a respective storage location within a storage row of the first memory. The state of one or more bits within the storage row of the first memory are changed based, at least in part, on the multiple-bit error value.

Abstract translation: 在集成电路设备内接收第一数据分组，并且在由第一地址开始的第一存储器内存储第一数据分组，该第一地址由一个或多个先前接收到的数据分组的大小确定。 错误描述符值在集成电路设备的第二存储器内被更新，错误描述符包括指示与第一数据包相关联的错误的错误字段，指示第一存储器内的第一地址的地址字段和 长度字段，指示应用错误的存储位置的范围。 至少部分地基于错误描述符生成多位错误值，所述多位错误值的每个位对应于第一存储器的存储行内的相应存储位置。 至少部分地基于多位错误值来改变第一存储器的存储行内的一个或多个位的状态。

公开(公告)号：WO2007008419A1

公开(公告)日：2007-01-18

申请号：PCT/US2006/025147

申请日：2006-06-28

Applicant: MICROCHIP TECHNOLOGY INCORPORATED ,  SAMUEL, Roshan, J. ,  ROJVANIT, Rawin

Inventor： SAMUEL, Roshan, J. ,  ROJVANIT, Rawin

IPC: H03M13/09

CPC classification number: H03M13/6516 ,  H03M13/09

Abstract: A method and apparatus for configuring a cyclic redundancy check (CRC) generation circuit to perform CRC on a data stream are disclosed. The method includes storing a generator polynomial associated with a CRC equation in a register, where the generator polynomial has a length capable of varying such that the length has any value less than or equal to a number of bits associated with a CRC generation circuit. A bit position of the CRC generation circuit that corresponds to the length of the generator polynomial is selected by using a first multiplexer to generate a feedback value. The CRC generation circuit is programmed to calculate a CRC checksum based on the generator polynomial stored in the register and the feedback value from the selected bit position.

Abstract translation: 公开了一种用于配置循环冗余校验（CRC）产生电路以对数据流执行CRC的方法和装置。 该方法包括将与CRC方程相关联的生成多项式存储在寄存器中，其中生成多项式具有能够变化的长度，使得长度具有小于或等于与CRC生成电路相关联的位数的任何值。 通过使用第一多路复用器来选择对应于生成多项式的长度的CRC生成电路的比特位置，以产生反馈值。 CRC生成电路被编程为基于存储在寄存器中的生成多项式和来自所选位位置的反馈值来计算CRC校验和。

公开(公告)号：WO2007003500A1

公开(公告)日：2007-01-11

申请号：PCT/EP2006/063305

申请日：2006-06-19

Applicant: SIEMENS AKTIENGESELLSCHAFT ,  FARKAS, Peter

Inventor： FARKAS, Peter

IPC: H04L1/00

CPC classification number: H03M13/47 ,  H03M13/09 ,  H03M13/1515 ,  H03M13/19 ,  H03M13/2957 ,  H03M13/635 ,  H04L1/0006 ,  H04L1/0045 ,  H04L1/0057

Abstract: The invention consists of an apparatus and a method for adapting data in a communications system to be transmitted from a sender to a receiver, to a transport unit of a predefined size comprising the steps of : - representing said data as a combination of bits over a finite field, wherein said data comprises of an information part and a control part; - adapting said represented data to fit said predefined size of said transport unit, by expressing both said information and control parts with bits, wherein said bits are less in number that said represented combination of bits and a number of removed bits is known to said receiver, said removed bits comprise of bits from both said information and control parts .

Abstract translation: 本发明包括一种用于使通信系统中的数据从发送方发送到接收机的装置和方法，其包括以下步骤： - 将所述数据表示为一个 有限域，其中所述数据包括信息部分和控制部分; - 通过用位表示所述信息和控制部分两者来适配所述表示的数据以适合所述传输单元的所述预定义大小，其中所述位的数量较少，所述表示的位组合和所述接收器的已知位数已知 所述去除的位包括来自所述信息和控制部分的位。

公开(公告)号：WO2006125157A2

公开(公告)日：2006-11-23

申请号：PCT/US2006/019456

申请日：2006-05-18

Applicant: TELEGENT SYSTEMS, INC. ,  GUO, Sharori

Inventor： GUO, Sharori

IPC: H03M13/15 ,  H03M13/09 ,  H04L1/00

CPC classification number: H03M13/09 ,  H04L1/0045 ,  H04L1/0057

Abstract: A first data packet is received within an integrated circuit device and stored within a first memory thereof starting at a first address that is determined by the size of one or more previously received data packets. An error descriptor value is updated within a second memory of the integrated circuit device, the error descriptor including an error field that indicates an error that is associated with the first data packet, an address field that indicates the first address within the first memory and a length field that indicates a range of storage locations to which the error applies. A multiple-bit error value is generated based, at least in part, on the error descriptor, each bit of the multiple-bit error value corresponding to a respective storage location within a storage row of the first memory. The state of one or more bits within the storage row of the first memory are changed based, at least in part, on the multiple-bit error value.

Abstract translation: 在集成电路设备内接收第一数据分组，并且在由第一地址开始的第一存储器内存储第一数据分组，该第一地址由一个或多个先前接收到的数据分组的大小确定。 错误描述符值在集成电路设备的第二存储器内被更新，错误描述符包括指示与第一数据包相关联的错误的错误字段，指示第一存储器内的第一地址的地址字段和 长度字段，指示应用错误的存储位置的范围。 至少部分地基于错误描述符生成多位错误值，所述多位错误值的每个位对应于第一存储器的存储行内的相应存储位置。 至少部分地基于多位错误值来改变第一存储器的存储行内的一个或多个位的状态。

公开(公告)号：WO2006123542A1

公开(公告)日：2006-11-23

申请号：PCT/JP2006/309202

申请日：2006-04-27

Applicant: CANON KABUSHIKI KAISHA ,  KANDA, Tetsuo ,  EGUCHI, Tadashi

Inventor： KANDA, Tetsuo ,  EGUCHI, Tadashi

IPC: H04L1/00

CPC classification number: H04L1/0057 ,  H03M13/09 ,  H03M13/11 ,  H03M13/3738 ,  H03M13/63 ,  H04L1/0045 ,  H04L1/0054 ,  H04L1/0061 ,  H04L1/0072

Abstract: A communication apparatus includes a plurality of descramblers for subjecting a second header portion of a received frame to descrambling processing using pseudo-random sequences that differ from one another; a plurality of syndrome arithmetic units for performing a syndrome calculation, which is in accordance with a cyclic redundancy check code, with respect to headers descrambled by respective ones of the plurality of descramblers, and an error correction unit for selecting a header that has been descrambled by one descrambler among the plurality of descramblers as a receive header, in accordance with syndrome values calculated by respective ones of the plurality of syndrome arithmetic units.

Abstract translation: 通信装置包括多个解扰器，用于使接收帧的第二报头部分使用彼此不同的伪随机序列进行解扰处理; 多个校正子运算单元，用于相对于由多个解扰器中的相应的解扰频器解扰的报头执行与循环冗余校验码相对应的校正子计算;以及纠错单元，用于选择已解扰的报头 根据由多个校正子运算单元中的各个算出单元计算出的校正子值，由多个解扰器之中的一个解扰器作为接收头。

公开(公告)号：WO2006003531A1

公开(公告)日：2006-01-12

申请号：PCT/IB2005/050950

申请日：2005-03-18

Applicant: NOKIA CORPORATION ,  VESMA, Jussi ,  PEKONEN, Harri

Inventor： VESMA, Jussi ,  PEKONEN, Harri

IPC: H04L1/00

CPC classification number: H03M13/293 ,  H03M13/09 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/6356 ,  H03M13/6362 ,  H04L1/0052 ,  H04L1/0057

Abstract: An erasure information table includes one element for each column of a data frame, stored in an IP datagram buffer 66 and in an RS data buffer 67, instead of an element for each element of that column. Thus, CRC checking is performed against datagrams, instead of individual elements, of a received data frame, and effective error correction can be carried out by a Reed Solomon decoder 69. The effectiveness of the error correction is decreased since errors will be indicated as being present when actually an error is present in another row. The amount of memory needed to store the erasure information though is reduced. In another embodiment (Figures 9 and 10), a linked list includes an element for each series of datagrams which have the same error status (i.e. reliable or unreliable). Each element includes the start address of the first datagram in that sequence and indicates the error status. Different lists may be used for application data and for parity data.

Abstract translation: 擦除信息表包括存储在IP数据报缓冲器66和RS数据缓冲器67中的数据帧的每列的一个元素，而不是该列的每个元素的元素。 因此，针对接收到的数据帧的数据报而不是单个元素执行CRC校验，并且可以由里德所罗门解码器69执行有效的纠错。纠错的有效性减小，因为错误将被表示为 当实际上在另一行中存在错误时出现。 存储擦除信息所需的内存量减少。 在另一实施例（图9和10）中，链表包括具有相同错误状态（即可靠或不可靠）的每一系列数据报的元素。 每个元素包括该序列中第一个数据报的起始地址，并指示错误状态。 不同的列表可用于应用程序数据和奇偶校验数据。