公开(公告)号：WO2022213058A1

公开(公告)日：2022-10-06

申请号：PCT/US2022/071391

申请日：2022-03-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： POHLMANN, Erik, V.

IPC: G11C11/4076 ,  G11C11/408 ,  G11C7/22 ,  G11C8/18 ,  G11C7/1063 ,  G11C7/1066 ,  G11C7/1093

Abstract: Methods, systems, and devices for dynamic random access memory speed bin compatibility are described. For instance, a device (e.g., a memory device, a host device) may combine a first parameter with a second parameter to generate a third parameter, where the first parameter may be associated with a duration for a clock that is coupled with a memory array to perform a clock cycle and the second parameter may be associated with a timing constraint associated with initiating an access operation for the memory array. The device may determine a latency of a column address strobe based on the third parameter relative to (e.g., satisfying) a threshold value and may access one or more memory cells of the memory array based on the latency of the column address strobe.

公开(公告)号：WO2022170304A1

公开(公告)日：2022-08-11

申请号：PCT/US2022/070389

申请日：2022-01-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： POHLMANN, Erik, V. ,  KOYLE, Neal, J.

IPC: G11C7/22 ,  G06F1/06 ,  G11C7/10

Abstract: Methods, systems, and devices for memory clock management and estimation procedures are described. A host device may determine a quantity of clock cycles associated with a duration for accessing a memory cell of a memory array based on truncating a value of a first parameter associated with another duration for a clock to perform a clock cycle. The host device may estimate a value of a second parameter related to (e.g., inversely proportional) to the truncated value of the first parameter and related to (e.g., directly proportional) to a correction factor, and may adjust (e.g., truncate) a third parameter to determine the quantity of clock cycles. Additionally or alternatively, the host device may adjust (e.g., perform a ceiling operation on) the second parameter to determine the quantity of clock cycles. The host device may access the memory cell based on the quantity of clock cycles.

公开(公告)号：WO2022046304A1

公开(公告)日：2022-03-03

申请号：PCT/US2021/041477

申请日：2021-07-13

Applicant: MICRON TECHNOLOGY, INC

Inventor： LU, Yang ,  STODDARD, Christopher Heaton

IPC: G11C7/22 ,  G11C7/10 ,  H03L7/081 ,  G06F3/06

Abstract: A memory system (10) is provided. The memory system (10) includes a memory system (22) and a data bus (24) electrically coupled to the memory system (22). The memory system (10) further includes one or more memory devices (12, 14, 16) communicatively coupled to the memory system (22) via the data bus (24), wherein each of the one or more memory devices (12, 14, 16) comprises a read training setting configured to adjust a read output timing of data being sent to the memory system (22) during read operations from the one or more memory devices (12, 14, 16).

公开(公告)号：WO2021225839A1

公开(公告)日：2021-11-11

申请号：PCT/US2021/029553

申请日：2021-04-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： HUSH, Glen E. ,  MURPHY, Richard C. ,  SUN, Honglin

IPC: G11C7/22 ,  G06F3/06 ,  G11C7/06

Abstract: Apparatuses and methods can be related to generating an asynchronous process topology in a memory device. The topology can be generated based on the results of a number of processes. The processes can be asynchronous given that the processing resources that implement the processes do not use a clock signal to generate the topology.

公开(公告)号：WO2021194676A1

公开(公告)日：2021-09-30

申请号：PCT/US2021/019259

申请日：2021-02-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： BOEHM, Aaron, P. ,  SCHAEFER, Scott, E.

IPC: G11C7/04 ,  G11C7/10 ,  G11C7/22 ,  G06F3/06 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0673 ,  G11C11/221 ,  G11C11/4087 ,  G11C11/4091 ,  G11C13/0004

Abstract: Methods, systems, and devices related to operating a memory array are described. A system may include a memory device and a host device. A memory device may indicate information about a temperature of the memory device, which may include sending an indication to the host device after receiving a signal that initializes the operation of the memory device or storing an indication, for example in a register, about the temperature of the memory device. The information may include an indication that a temperature of the memory device or a rate of change of the temperature of the memory device has satisfied a threshold. Operation of the memory device, or the host device, or both may be modified based on the information about the temperature of the memory device. Operational modifications may include delaying a sending or processing of memory commands until the threshold is satisfied.

公开(公告)号：WO2021178590A1

公开(公告)日：2021-09-10

申请号：PCT/US2021/020745

申请日：2021-03-03

Applicant: QUALCOMM INCORPORATED

Inventor： LEE, Hochul ,  KOTA, Anil Chowdary ,  KIM, Keejong

IPC: G11C17/18 ,  G11C7/22 ,  G11C16/34 ,  G11C17/14 ,  G11C17/16 ,  G11C29/02

Abstract: A One Time Programmable (OTP) memory, includes: a first driver coupled to a reference cell by a first bit line; a second driver coupled to an OTP cell by a second bit line; and a comparator having a first input coupled to the first bit line and the reference cell, a second input coupled to the second bit line and the OTP cell, and an output coupled to a logic circuit configured to control the first driver and the second driver.

公开(公告)号：WO2021173943A1

公开(公告)日：2021-09-02

申请号：PCT/US2021/019833

申请日：2021-02-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： BARRY, Beau D.

IPC: G11C8/06 ,  G11C8/18 ,  G11C8/08 ,  G11C8/10 ,  G11C7/10 ,  G11C7/22 ,  G11C7/06

Abstract: Apparatuses, systems, and methods for address based memory performance, A memory array may include a first performance region and a second performance region, each of which may have different performance characteristics from each other. The second region may be distinguished from the first region based on the addresses which are associated with each region. The second performance region may have different performance characteristics based on differences in the layout, components, logic circuits, and combinations thereof. For example, the second region, compared to the first region, may have reduced difference to the data terminals, reduced length of digit lines, a different type of sense amplifier, different refresh address tracking, and combinations thereof. The controller may perform access operations on the memory with different timing based on which region of the memory is accessed.

公开(公告)号：WO2021126660A1

公开(公告)日：2021-06-24

申请号：PCT/US2020/064249

申请日：2020-12-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： JOHNSON, James, Brian

IPC: G11C7/22 ,  G11C7/10 ,  G06F3/06 ,  G06F1/10 ,  G06F1/12 ,  G11C7/1006 ,  G11C7/1072

Abstract: Methods, systems, and devices for clock locking for frame-based communications of memory devices are described. A memory system may include a memory device and a host device. The memory device may receive one or more frames of data from the host device, the one or more frames of data communicated by the host device using a first frame clock. The memory device may generate a second frame clock aligned with the one or more frames on receiving the one or more frames and align one or more operations of the memory device with the second frame clock. In some examples, the host device may receive a second set of frames from the memory device based on transmitting the first set of frames. The host device may align one or more operations of the host device with the second set of frames received from the memory device.

公开(公告)号：WO2021101208A1

公开(公告)日：2021-05-27

申请号：PCT/KR2020/016166

申请日：2020-11-17

Applicant: 주식회사 메타씨앤아이

Inventor： 김영승 ,  유승문 ,  정민철

IPC: G11C7/22 ,  G11C7/06 ,  H03K5/1534

Abstract: 본 발명에 따른 메모리 장치는, 메모리 셀들이 워드 라인들과 비트 라인들에 매트릭스 형태로 연결된 메모리 셀 어레이; 메모리 셀 어레이에 포함된 메모리 셀 중에서 선택된 메모리 셀로부터 읽혀 직류 형태와 펄스 형태 중 하나로 변형된 데이터를 전달하도록 연쇄적으로 연결되는 복수 개의 병합기; 및 복수 개의 병합기 중 하나가 출력하는 제1 출력 데이터의 에지를 제어 펄스의 에지에 동기하여 지연시키는 정렬기를 포함하여 구성될 수 있다. 데이터 비트 '0'과 데이터 비트 '1' 중 하나인 제1 데이터는 제1 로직의 직류 형태로, 다른 하나인 제2 데이터는 제1 로직에서 제2 로직을 거쳐 다시 제1 로직으로 바뀌는 펄스 형태로, 병합기에 입력될 수 있다. 정렬기는, 제1 데이터가 입력될 때 제1 데이터를 그대로 통과시켜 제1 로직의 직류 형태의 제2 출력 데이터로 출력하고, 제2 로직에서 제1 로직으로 바뀌는 제1 에지가 입력될 때 제1 에지를 제어 펄스의 상승 에지 또는 하강 에지에 동기하여 지연시켜 제2 출력 데이터로 출력할 수 있다.

公开(公告)号：WO2021087226A1

公开(公告)日：2021-05-06

申请号：PCT/US2020/058152

申请日：2020-10-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MCGLAUGHLIN, Edward

IPC: G11C7/10 ,  G11C7/22

Abstract: A memory sub-system includes a memory sub-system controller comprising at least one host channel, a memory device comprising a plurality of memory die, and at least one input/output (I/O) expander circuit coupled to the at least one host channel of the memory sub-system controller and to the memory device. The at least one I/O expander circuit includes one or more I/O buffers to send and receive signals on the at least one host channel, a selection circuit coupled to the one or more I/O buffers, and command processing logic to enable the selection circuit to route the signals on a selected one of a plurality of expansion channels coupled to the at least one I/O expander circuit. Each of the plurality of expansion channels is coupled to a corresponding subset of the plurality of memory die.