公开(公告)号：WO2021225839A1

公开(公告)日：2021-11-11

申请号：PCT/US2021/029553

申请日：2021-04-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： HUSH, Glen E. ,  MURPHY, Richard C. ,  SUN, Honglin

IPC: G11C7/22 ,  G06F3/06 ,  G11C7/06

Abstract: Apparatuses and methods can be related to generating an asynchronous process topology in a memory device. The topology can be generated based on the results of a number of processes. The processes can be asynchronous given that the processing resources that implement the processes do not use a clock signal to generate the topology.

公开(公告)号：WO2021225838A1

公开(公告)日：2021-11-11

申请号：PCT/US2021/029547

申请日：2021-04-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： HUSH, Glen E. ,  MURPHY, Richard C. ,  SUN, Honglin

IPC: G06F13/40 ,  G06F3/06 ,  G06F13/42

Abstract: Apparatuses and methods can be related to configuring interface protocols for memory. An interface protocol can define the commands received by a memory device utilizing transceivers, receivers, and/or transmitters of an interface of a memory device. An interface protocol used by a memory device can be implemented utilizing a decoder of signals provided via a plurality of transceivers of the memory device. The decoder utilized by a memory device can be selected by setting a mode register of the memory device.

公开(公告)号：WO2021041109A1

公开(公告)日：2021-03-04

申请号：PCT/US2020/046959

申请日：2020-08-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： SUN, Honglin ,  MURPHY, Richard C. ,  HUSH, Glen E.

IPC: G11C7/10 ,  G11C7/06 ,  G06F12/0802

Abstract: Apparatuses and methods can be related to performing operations in memory. Operations can be performed in the background while the memory is performing different operations. For example, comparison operations can be performed by the memory device while the memory device is reading data. The results of the comparison operations can be stored in registers of the memory device. The registers can be made accessible externally to the memory device.

公开(公告)号：WO2021178631A1

公开(公告)日：2021-09-10

申请号：PCT/US2021/020817

申请日：2021-03-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MURPHY, Richard C. ,  HUSH, Glen E. ,  SUN, Honglin

IPC: G06F13/38 ,  G06F3/06 ,  G06F13/16

Abstract: Apparatuses and methods can be related to configuring interface protocols for memory. An interface protocol can define the commands received by a memory device utilizing pins of an interface of a memory device. An interface protocol used by a memory device can be implemented utilizing a decoder of signals provided through the pins of the memory device. The decoder utilized by a memory device can be selected by setting a mode register of the memory device.

公开(公告)号：WO2021029941A1

公开(公告)日：2021-02-18

申请号：PCT/US2020/036299

申请日：2020-06-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MURPHY, Richard C. ,  HUSH, Glen E. ,  SUN, Honglin

IPC: G06N3/063 ,  G06N3/04

Abstract: Systems, apparatuses, and methods related to multiple artificial neural networks (ANNs) in memory. Such ANNs can be implemented within a memory system (including a number of memory devices) at different granularities. For example, multiple ANNs can be implemented within a single memory device and/or a single ANN can be implemented over multiple memory devices (such that multiple memory devices are configured as a single ANN). The memory system having multiple ANNs can operate each ANN independently from each other such that multiple ANN operations can be concurrently performed.

公开(公告)号：WO2021041390A1

公开(公告)日：2021-03-04

申请号：PCT/US2020/047764

申请日：2020-08-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MURPHY, Richard C. ,  HUSH, Glen E. ,  SUN, Honglin

IPC: G06N3/063 ,  G06N3/04 ,  G06N3/08 ,  G11C11/406 ,  G11C11/4063

Abstract: Devices and methods related to spiking neural units in memory. One device includes a memory array and a complementary metal-oxide semiconductor (CMOS) coupled to the memory array and located under the memory array, wherein the CMOS includes a spiking neural unit comprising logic configured to receive an input to increase a weight stored in a memory cell of the memory array, collect the weight from the memory cell of the memory array, accumulate the weight with an increase based on the input, compare the accumulated weight to a threshold weight, and provide an output in response to the accumulated weight being greater than the threshold weight.

公开(公告)号：WO2021021288A1

公开(公告)日：2021-02-04

申请号：PCT/US2020/036304

申请日：2020-06-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： HUSH, Glen, E. ,  SUN, Honglin ,  MURPHY, Richard, C.

IPC: G11C7/06 ,  G11C7/10 ,  G06F3/06

Abstract: Systems, apparatuses, and methods related to performing operations within a memory device are described. Such operations may be performed using data latched in multiple sense amplifiers that are distributed among a plurality of sense amplifiers of the memory device. For example, those sense amplifiers, among the plurality of sense amplifiers, storing data associated with the operation(s) can be determined, and the data can be selectively sent from the determined sense amplifiers to an operation unit, in which the operations are performed. The operations may be made without affecting a subsequent read command that requests data from the plurality of sense amplifiers.

公开(公告)号：WO2022020140A1

公开(公告)日：2022-01-27

申请号：PCT/US2021/041457

申请日：2021-07-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： HUSH, Glen E. ,  MURPHY, Richard C. ,  SUN, Honglin

IPC: G11C7/06 ,  G11C7/10 ,  G06F15/173 ,  G06F12/0802

Abstract: Apparatuses and methods can be related to implementing edge compute components in a memory array. Compute components can be implemented under a memory array. Implementing compute components under a memory array can limit control access to the compute components due to die space utilized by the compute components. A portion of the compute components (e.g., compute components on the edge) may have control access that is not available to the remainder of the compute components.

公开(公告)号：WO2021034912A1

公开(公告)日：2021-02-25

申请号：PCT/US2020/046965

申请日：2020-08-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： SUN, Honglin ,  MURPHY, Richard C. ,  HUSH, Glen E.

IPC: G06F3/06 ,  G06F13/16 ,  G06N3/063 ,  G06N20/00

Abstract: Apparatuses and methods can be related to supplementing AI processing in memory. An accelerator and/or a host can perform AI processing. Some of the operations comprising the AI processing can be performed by a memory device instead of by an accelerator and/or a host. The memory device can perform AI processing in conjunction with the host and/or accelerator to increase the efficiency of the host and/or accelerator.

公开(公告)号：WO2021025812A1

公开(公告)日：2021-02-11

申请号：PCT/US2020/040479

申请日：2020-07-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： SUN, Honglin ,  HUSH, Glen E. ,  MURPHY, Richard C.

IPC: G06F21/32 ,  G06F3/00 ,  G06F3/06 ,  G06F13/16 ,  G06K9/00 ,  G06N3/08

Abstract: Systems, apparatuses, and methods related to comparison of biometric identifiers in memory are described. An example apparatus includes an array of memory cells, a plurality of logic blocks in complementary metal-oxide-semiconductor (CMOS) under the array, and a controller coupled to the array of memory cells. The controller is configured to control a first portion of the plurality of logic blocks to receive a first subset of a set of biometric identifiers from the array and to perform a first comparison operation thereon and control a second portion of the logic blocks to receive a second subset of the set of biometric identifiers from the array and to perform a second comparison operation thereon. The first and second subsets of the biometric identifiers are different biometric identifiers and the first and second comparison operations are performed to determine a match of the first and second subsets respectively to a stored template.