公开(公告)号：WO2022150121A1

公开(公告)日：2022-07-14

申请号：PCT/US2021/061436

申请日：2021-12-01

申请人： MICRON TECHNOLOGY, INC.

发明人： RAMESH, Vijay S. ,  MURPHY, Richard C.

IPC分类号： G06N3/063 ,  G06N3/04 ,  G06F3/06 ,  G06F13/16

摘要： Methods, systems, and apparatuses related to a memory system to train neural networks are described. For example, data management and training of one or more neural networks may be accomplished within multiple memory devices. Neural networks may thus be trained in the absence of specialized circuitry and/or in the absence of vast computing resources. A method includes performing at least a portion of a training operation for a neural network, on a first memory device, by determining one or more first weights for a hidden layer of the neural network and writing the data corresponding to the neural network to a second memory device. The method further includes performing, using the data corresponding to the neural network written to the second memory device, at least a second portion of the training operation for the neural network by determining one or more second weights for the hidden layer of the neural network.

公开(公告)号：WO2021041390A1

公开(公告)日：2021-03-04

申请号：PCT/US2020/047764

申请日：2020-08-25

申请人： MICRON TECHNOLOGY, INC.

发明人： MURPHY, Richard C. ,  HUSH, Glen E. ,  SUN, Honglin

IPC分类号： G06N3/063 ,  G06N3/04 ,  G06N3/08 ,  G11C11/406 ,  G11C11/4063

摘要： Devices and methods related to spiking neural units in memory. One device includes a memory array and a complementary metal-oxide semiconductor (CMOS) coupled to the memory array and located under the memory array, wherein the CMOS includes a spiking neural unit comprising logic configured to receive an input to increase a weight stored in a memory cell of the memory array, collect the weight from the memory cell of the memory array, accumulate the weight with an increase based on the input, compare the accumulated weight to a threshold weight, and provide an output in response to the accumulated weight being greater than the threshold weight.

公开(公告)号：WO2020197620A1

公开(公告)日：2020-10-01

申请号：PCT/US2020/015293

申请日：2020-01-28

申请人： MICRON TECHNOLOGY, INC.

发明人： MURPHY, Richard C. ,  HUSH, Glen E. ,  RAMESH, Vijay S. ,  PORTERFIELD, Allan ,  KORZH, Anton

IPC分类号： G06F9/30

摘要： Systems, apparatuses, and methods related to extended memory operations are described. Extended memory operations can include operations specified by a single address and operand and may be performed by a computing device that includes a processing unit and a memory resource. The computing device can perform extended memory operations on data streamed through the computing tile without receipt of intervening commands. In an example, a computing device is configured to receive a command to perform an operation that comprises performing an operation on a data with the processing unit of the computing device and determine that an operand corresponding to the operation is stored in the memory resource. The computing device can further perform the operation using the operand stored in the memory resource.

公开(公告)号：WO2019125796A8

公开(公告)日：2019-06-27

申请号：PCT/US2018/064658

申请日：2018-12-10

申请人： MICRON TECHNOLOGY, INC.

发明人： HUSH, Glen E. ,  MURPHY, Richard C.

IPC分类号： G11C8/06 ,  G11C7/10

摘要： Systems, apparatuses, and methods related to subrow addressing for electronic memory and/or storage are described. Independent subrow addressing may enable energy consumed by performance of an operation on a particular subset of data values stored by a row to more closely correspond to the size of the particular subset of data values relative to energy consumed by addressing and activating the complete row. For instance, one such apparatus includes a plurality of subrows within a row of memory cells and a controller configured to selectably address and manage an activation state of each subrow of the plurality of subrows. The apparatus further includes subrow driver circuitry coupled to the controller. The subrow driver circuitry is configured to maintain one or more subrows of the plurality in the activation state based at least in part on signaling from the controller.

公开(公告)号：WO2016126478A1

公开(公告)日：2016-08-11

申请号：PCT/US2016/015059

申请日：2016-01-27

申请人： MICRON TECHNOLOGY, INC.

发明人： ZAWODNY, Jason T. ,  WHEELER, Kyle B. ,  MURPHY, Richard C.

IPC分类号： G11C7/06 ,  G11C11/413 ,  G11C11/416

CPC分类号： G06F12/0238 ,  G06F12/0888 ,  G06F15/7821 ,  G06F2212/202 ,  G06F2212/603 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1036 ,  G11C8/12 ,  G11C11/4087 ,  G11C11/4096

摘要： The present disclosure includes apparatuses and methods related to a memory device as the store to program instructions. An example apparatus comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller, coupled to the array and the sensing circuitry is configured to receive a block of instructions including a plurality of program instructions. The memory controller is configured to store the block of instructions in the array and retrieve program instructions to perform logical operations on the compute component.

摘要翻译： 本公开包括与作为用于编程指令的存储器的存储器件相关的装置和方法。 示例性装置包括具有存储器单元阵列和耦合到阵列的感测电路的存储器件。 感测电路包括读出放大器和被配置为实现逻辑运算的计算组件。 耦合到阵列和感测电路的存储器控​​制器被配置为接收包括多个程序指令的指令块。 存储器控制器被配置为将指令块存储在阵列中并检索程序指令以对计算组件执行逻辑运算。

公开(公告)号：WO2022005673A1

公开(公告)日：2022-01-06

申请号：PCT/US2021/035125

申请日：2021-06-01

申请人： MICRON TECHNOLOGY, INC.

发明人： RAMESH, Vijay S. ,  MURPHY, Richard C.

IPC分类号： G06N3/063 ,  G06N3/04 ,  G06F7/544 ,  G11C11/54

摘要： Systems, apparatuses, and methods related to a neuron built with posits are described. An example system may include a memory device and the memory device may include a plurality of memory cells. The plurality of memory cells can store data including a bit string in an analog format. A neuromorphic operation can be performed on the data in the analog format. The example system may include an analog to digital converter coupled to the memory device. The analog to digital converter may convert the bit string in the analog format stored in at least one of the plurality of memory cells to a format that supports arithmetic operations to a particular level of precision.

公开(公告)号：WO2021225838A1

公开(公告)日：2021-11-11

申请号：PCT/US2021/029547

申请日：2021-04-28

申请人： MICRON TECHNOLOGY, INC.

发明人： HUSH, Glen E. ,  MURPHY, Richard C. ,  SUN, Honglin

IPC分类号： G06F13/40 ,  G06F3/06 ,  G06F13/42

摘要： Apparatuses and methods can be related to configuring interface protocols for memory. An interface protocol can define the commands received by a memory device utilizing transceivers, receivers, and/or transmitters of an interface of a memory device. An interface protocol used by a memory device can be implemented utilizing a decoder of signals provided via a plurality of transceivers of the memory device. The decoder utilized by a memory device can be selected by setting a mode register of the memory device.

公开(公告)号：WO2021133826A1

公开(公告)日：2021-07-01

申请号：PCT/US2020/066664

申请日：2020-12-22

申请人： MICRON TECHNOLOGY, INC.

发明人： KEETH, Brent ,  ROSS, Frank F. ,  MURPHY, Richard C.

IPC分类号： G06N3/063 ,  G06N3/04 ,  G06N3/08 ,  G11C11/54 ,  G06F13/1668 ,  G06N3/004 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18

摘要： Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a stack of memory dies, a controller die, and a buffer. Example memory devices, systems and methods include one or more neuromorphic layers logically coupled between one or more dies in the stack of memory dies and a host interface of the controller die.

公开(公告)号：WO2021041109A1

公开(公告)日：2021-03-04

申请号：PCT/US2020/046959

申请日：2020-08-19

申请人： MICRON TECHNOLOGY, INC.

发明人： SUN, Honglin ,  MURPHY, Richard C. ,  HUSH, Glen E.

IPC分类号： G11C7/10 ,  G11C7/06 ,  G06F12/0802

摘要： Apparatuses and methods can be related to performing operations in memory. Operations can be performed in the background while the memory is performing different operations. For example, comparison operations can be performed by the memory device while the memory device is reading data. The results of the comparison operations can be stored in registers of the memory device. The registers can be made accessible externally to the memory device.

公开(公告)号：WO2021034599A1

公开(公告)日：2021-02-25

申请号：PCT/US2020/046148

申请日：2020-08-13

申请人： MICRON TECHNOLOGY, INC.

发明人： KORZH, Anton ,  RAMESH, Vijay S. ,  MURPHY, Richard C.

IPC分类号： G06F13/16 ,  G06F9/455 ,  G06F12/02 ,  G06F12/1036 ,  G06F13/42

摘要： Apparatuses, systems, and methods for hierarchical memory systems are described. A hierarchical memory system can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. An example method includes initiating a read request associated with an address from an input/output device, redirecting the read request to a hierarchical memory component, generating, by the hierarchical memory component, an interrupt message to send to a hypervisor, gathering, at the hypervisor, address register access information from the hierarchical memory component, and determining a physical location of data associated with the read request.