公开(公告)号：WO1982003737A1

公开(公告)日：1982-10-28

申请号：PCT/US1981000497

申请日：1981-04-16

申请人： MOSTEK CORP ,  PROEBSTING ROBERT J

发明人： MOSTEK CORP

IPC分类号： H03K19/094

CPC分类号： H03K19/00315 ,  H03K19/09429

摘要： A current limiting driver circuit (10) receives a first logic level input signal (O &cir& /1) and drives an output pin (26). A node (14) is pulled to ground by a pull-down transistor (16) which receives the first input signal (O &cir& /1) and is driven to a high voltage state by a pull-up transistor (12). A driver transistor (28) is turned on by a high voltage state at the node (14) and is turned off by a low voltage state at the node (14). The driver transistor (28) is connected to provide a high voltage state to the output pin (26). A pull-down transistor (30) is connected to receive the first input signal (O &cir& /1) in order to pull the output pin (26) to ground. A series of transistors (18, 20, 22) are connected between the gate and source terminals of the driver transistor (28) such that when the gate-to-source voltage of the driver transistor (28) exceeds the combined thresholds of the three transistors (18, 20, 22) they will by turned on and thereby limit the maximum gate-to-source voltage of driver transistor (28). This in turn serves to limit the maximum current flow through the driver transistor (28). Disabling transistors (17, 32) are included for providing a high impedance output to the output pin (26).

摘要翻译： 电流限制驱动器电路（10）接收第一逻辑电平输入信号（O＆CIR1）并驱动输出引脚（26）。 节点（14）被接收第一输入信号（O和CIR1）的下拉晶体管（16）拉到地，并被上拉晶体管（12）驱动到高电压状态。 驱动晶体管（28）在节点（14）处通过高电压状态导通，并且在节点（14）处由低电压状态断开。 驱动晶体管（28）被连接以向输出引脚（26）提供高电压状态。 连接下拉晶体管（30）以接收第一输入信号（O和CIR），以便将输出引脚（26）拉到地。 一系列晶体管（18,20,22）连接在驱动晶体管（28）的栅极和源极端子之间，使得当驱动晶体管（28）的栅极 - 源极电压超过三个 晶体管（18,20,22）将导通，从而限制驱动晶体管（28）的最大栅极 - 源极电压。 这又用于限制通过驱动晶体管（28）的最大电流。 包括禁止晶体管（17,32），用于向输出引脚（26）提供高阻抗输出。

公开(公告)号：WO1982002277A1

公开(公告)日：1982-07-08

申请号：PCT/US1980001725

申请日：1980-12-24

申请人： MOSTEK CORP ,  LARSON DAVID NATHANIEL

发明人： MOSTEK CORP

IPC分类号： G11C11/40

CPC分类号： G11C11/412

摘要： A memory cell (10) for storing data having a data line (12) and a bit enable line (16) for receiving control signals. First and second signal lines (24, 26) receive control signals. A first transistor (14) is interconnected to the data line (12) and to the bit enable line (16). A second transistor (20) is connected to the first transistor (14) and to the first control line (24). A third transistor (22) is connected to the first transistor (14) and to the second control line (26). A first inverter (30) is interconnected to the second transistor (20) to form a first node (34) and to the third transistor (22) to form a second node (36). A second inverter (32) is interconnected between the first node (34) and the second node (36).

摘要翻译： 一种用于存储具有用于接收控制信号的数据线（12）和位使能线（16）的数据的存储单元（10）。 第一和第二信号线（24,26）接收控制信号。 第一晶体管（14）与数据线（12）和位使能线（16）互连。 第二晶体管（20）连接到第一晶体管（14）和第一控制线（24）。 第三晶体管（22）连接到第一晶体管（14）和第二控制线（26）。 第一逆变器（30）与第二晶体管（20）互连以形成第一节点（34）和第三晶体管（22）以形成第二节点（36）。 第二逆变器（32）在第一节点（34）和第二节点（36）之间互连。

公开(公告)号：WO1982001102A1

公开(公告)日：1982-04-01

申请号：PCT/US1980001184

申请日：1980-09-15

申请人： MOSTEK CORP ,  MULHOLLAND W

发明人： MOSTEK CORP

IPC分类号： H01L23/48

CPC分类号： H01L23/5286 ,  H01L23/4824 ,  H01L24/06 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/00

摘要： A power distribution network for an integrated circuit is fabricated together with the circuit on a silicon substrate (10). The silicon substrate (10) is fabricated to form diffusion regions (50) as part of the active devices in the integrated circuit. A dielectric separation layer (51) is fabricated over the surface of substrate (10). Above the region (50) there is fabricated a power distribution line (52) comprising a metallization of aluminum or aluminum-alloy material. A passivation layer (54) is formed over the dielectric layer (51) and the conductor (52) but is opened above the central region of the conductor (52). An adhesion and diffusion barrier layer (58) is fabricated over the conductor (52) and passivation layer (54). Above the layer (58) there is fabricated a thick layer of metallization (60) in the form of a conductor strip configured similar to the underlying conductor layer (52). The conductive layers (58, 60) are etched to have essentially the same width as the conductor line (52). The conductive layers (58 and 60) can optionally be made to have a greater width than the underlying layer as is illustrated by the conducting layers (76, 78).

摘要翻译： 与硅衬底（10）上的电路一起制造用于集成电路的配电网络。 制造硅衬底（10）以形成作为集成电路中的有源器件的一部分的扩散区（50）。 在衬底（10）的表面上制造介电分离层（51）。 在区域（50）之上，制造包括铝或铝合金材料的金属化的配电线（52）。 钝化层（54）形成在电介质层（51）和导体（52）之上，但是在导体（52）的中心区域上方开口。 在导体（52）和钝化层（54）之上制造粘附和扩散阻挡层（58）。 在层（58）之上，制造了类似于下面的导体层（52）的导体条形式的厚的金属化层（60）。 导电层（58,60）被蚀刻以具有与导体线（52）基本相同的宽度。 导电层（58和60）可以可选地被制成具有比下层更大的宽度，如由导电层（76,78）所示。

公开(公告)号：WO1982000915A1

公开(公告)日：1982-03-18

申请号：PCT/US1980001162

申请日：1980-09-10

申请人： MOSTEK CORP ,  PLACHNO R ,  JIANG C

发明人： MOSTEK CORP

IPC分类号： G11C07/00

CPC分类号： G11C11/406

摘要： A clocking system for a self-refreshed dynamic memory (10) for reading data stored in a memory cell (30) and including clocking circuitry (68) includes detecting changes in an address signal (60). The method further includes generating a memory refresh signal (64, 66) in response to detecting changes in the address signal (60). The memory refresh signal (66) is applied to the semiconductor memory circuit (30) for refreshing data stored in the memory cells of the semiconductor memory circuit (30). After the application of the memory refresh signal (66) to the semiconductor memory circuit (30) the address signal (16) is applied to the semiconductor memory circuit (30) for accessing the addressed memory cell to thereby read the data stored therein. The clocking circuitry (68) is reset and precharged during the application of the refresh signal (66) to the semiconductor memory circuit (30).

摘要翻译： 用于读取存储在存储单元（30）中并包括时钟电路（68）的数据的自刷新动态存储器（10）的计时系统包括检测地址信号（60）中的变化。 该方法还包括响应于检测到地址信号（60）中的变化而产生存储器刷新信号（64,66）。 存储器刷新信号（66）被施加到半导体存储器电路（30），用于刷新存储在半导体存储器电路（30）的存储单元中的数据。 在向半导体存储器电路（30）施加存储器刷新信号（66）之后，将地址信号（16）施加到半导体存储器电路（30），以访问所寻址的存储器单元，从而读取存储在其中的数据。 在刷新信号（66）施加到半导体存储器电路（30）期间，时钟电路（68）被复位并被预充电。

公开(公告)号：WO1982000231A1

公开(公告)日：1982-01-21

申请号：PCT/US1980000817

申请日：1980-06-30

申请人： MOSTEK CORP ,  HOLBERG D

发明人： MOSTEK CORP

IPC分类号： H04M01/50

CPC分类号： H04M1/505

摘要： A dual-tone multi-frequency (DTMF) tone generator circuit (10) produces selected frequency row and column tones which are combined to generate a DTMF signal. Key board scan circuits (42, 44) scan a conventional push-button telephone key board to produce row and column input signals. Row and column fundamental rate signals are generated by fundamental counters (48, 76) from a reference signal derived from an external crystal (12). Row and column integration rate signals are generated by integrator counters (50, 78) also derived from the reference signal. Specialized row and column clock control signals (SLOPE RATE, SLOPE SIGN, AUTO ZERO) are produced by clock generators (58, 82). Row and column integrators (64, 92) integrate reference signals to produce discrete voltage steps at the rate of the row and column integration rate signals to produce row and column signals made up of a plurality of segments for each cycle of the signal. Each signal segment comprises a plurality of similar voltage steps having amplitude and polarity determined by the specialized row and column clock signals (SLOPE RATE, SLOPE SIGN). The row and column signals are combined in a summer (68) to produce the DTMF signal.

摘要翻译： 双音多频（DTMF）音产生器电路（10）产生被组合以产生DTMF信号的所选频率行和列音调。 键板扫描电路（42,44）扫描传统的按钮电话键盘以产生行和列输入信号。 行和列基本速率信号由基本计数器（48,76）从源自外部晶体（12）的参考信号产生。 行和列积分率信号由也从参考信号导出的积分器计数器（50,78）产生。 专门的行和列时钟控制信号（SLOPE RATE，SLOPE SIGN，AUTO ZERO）由时钟发生器（58,82）产生。 行和列积分器（64,92）集成参考信号以以行和列积分速率信号的速率产生离散电压步长，以产生由信号的每个周期的多个段组成的行和列信号。 每个信号段包括具有由专门的行和列时钟信号（SLOPE RATE，SLOPE SIGN）确定的振幅和极性的多个相似的电压阶跃。 行和列信号在夏季（68）中组合以产生DTMF信号。

公开(公告)号：WO1981002367A1

公开(公告)日：1981-08-20

申请号：PCT/US1980000662

申请日：1980-05-22

申请人： MOSTEK CORP

发明人： MOSTEK CORP ,  ANTES A

IPC分类号： H01L23/02

CPC分类号： H01L23/057 ,  H01L23/498 ,  H01L23/5383 ,  H01L2224/48091 ,  H01L2924/19107 ,  H01L2924/00014

摘要： Electronic circuit package (10) for encapsulating and interconnecting two or more semiconductor chips (44A). A vertically stacked array of substrate wafers form a support core (12) in which windows (14, 16, 18, 20) are formed for receiving the chips. Device support surfaces and device lead connecting surfaces (70, 72) are exposed by each cavity on one or more of the substrate wafers. Intra-level conductive strips (74) are separately deposited on each lead connecting surface for attachment to the input/output leads (42) of the circuit devices and extend along the interface of one or more superposed pairs of substrate wafers for connection to external connector pins. Inter-level conductive interconnects (78) are embedded in one or more of the substrates for interconnecting the intra-level conductive strips of one substrate level with the intra-level conductive strips of a different level. In a preferred embodiment, four identical RAM chips are encapsulated and interconnected for multiplex operation in an over/under, dual in-line arrangement.

公开(公告)号：WO1981002360A1

公开(公告)日：1981-08-20

申请号：PCT/US1980000653

申请日：1980-05-22

申请人： MOSTEK CORP

发明人： MOSTEK CORP ,  TAYLOR D ,  MCKENNY V

IPC分类号： G11C11/40

CPC分类号： G11C29/80

摘要： Block redundancy is utilized to improve yield and lower die cost for an electrically programmable read only memory (EPROM). The EPROM is organized 8Kx8 with four primary memory blocks (12A, 12B, 12C, 12D) on each side of a central row decoder. Each block includes an array (M) of memory cells, column select (CS), solumn decode (CD), sense amp (SA), data buffer (DB) and other overhead circuitry. One block of redundant circuitry (12RB - 1) is also provided for each set of four blocks and includes a redundant memory matrix (RM), a redundant column decoder (RCD), a redundant column select (RCS), a redundant sense amp (RSA) and a redundant data buffer (RDB). Incorporated with each primary memory block is a multiplex logic circuit (MUX) which is independently programmable to selectively disconnect the associated primary memory block and substitute the redundant memory block, including the redundant column decoder, column select, sense amp and data buffer. Each multiplex logic circuit (26) includes a polysilicon fuse (30) which is permanently programmable from a closed to an open circuit condition by applying a high voltage to the external data bit terminal (P1) which corresponds with the detective memory block cells.

公开(公告)号：WO1981002359A1

公开(公告)日：1981-08-20

申请号：PCT/US1981000147

申请日：1981-02-04

申请人： MOSTEK CORP

发明人： MOSTEK CORP ,  GRAHAM A

IPC分类号： G11C07/00

CPC分类号： G11C5/146 ,  G11C5/141 ,  Y10T307/615

摘要： A battery backup circuit for an MOS memory which has a multiplexed pin ((Alpha)WE) that functions to provide backup power to a memory cell array (50) upon loss of primary power Vcc. A voltage comparator (10) detects when the primary power Vcc becomes less than the backup voltage on the (Alpha)WE terminal. Upon detection of loss of primary power the memory cell array (50) is powered by a connection to the (Alpha)WE terminal. A primary power status signal ((Alpha)POK) indicates the status of the primary power and is driven to a state indicating insufficient circuit voltage for normal operation when Vcc drops below an acceptable limit or when there is inadequate substrate bias. The circuit of the present invention further generates an inhibit signal to prevent the operation of peripheral circuits (70) to write data into the memory cell array (50) upon detection of a failure of primary power. The inhibit signal is generated when primary power is lost or when the substrate bias is inadequate. A low-power auxiliary pump generator (92) provides a sufficient substrate bias to maintain the data pattern in the memory cell array (50) during the backup mode.

公开(公告)号：WO1981002080A1

公开(公告)日：1981-07-23

申请号：PCT/US1980000505

申请日：1980-05-05

申请人： MOSTEK CORP

发明人： MOSTEK CORP ,  JOHNSON C ,  YOUNG I ,  HILDEBRAND D

IPC分类号： H03K23/22

CPC分类号： H03K23/425 ,  H03K3/356078 ,  H03K19/01855 ,  H03K19/096

摘要： A logic circuit (20) is provided for receiving an input signal and for generating a delayed output signal being clocked by first and second non-overlapping clock phases. Logic circuit (20) includes a voltage supply (V). A precharge transistor (30) is interconnected to the voltage supply (V) and is clocked by the first clock phase. A discharge transistor (32) is interconnected to the precharge transistor (30) thereby defining a first node (A) and is clocked by the second clock phase to conditionally discharge the first node (A). An input logic circuit (34) is interconnected to the discharge transistor (32) thereby defining a second node (B) for providing a discharge path from the first node (A) to a ground voltage potential, the input logic circuit (34) is connected to receive the input signal. An output transistor (36) is interconnected to the first node (A) for generating the delayed output signal. The output transistor (36) is clocked by the second clock phase. A capacitor (38) is interconnected to the first node (A) and the output transistor (36) and is clocked by the second clock phase for maintaining the first node (A) at a predetermined voltage level by a bootstrapping operation.

公开(公告)号：WO1982002298A1

公开(公告)日：1982-07-08

申请号：PCT/US1980001724

申请日：1980-12-24

申请人： MOSTEK CORP ,  LARSON DAVID NATHANIEL ,  IRELAND JEFFREY RAY ,  TERRY MICHAEL BUFORD

发明人： MOSTEK CORP

IPC分类号： H03K03/023

CPC分类号： H03K4/501

摘要： A resistor-capacitor oscillator circuit (10) is provided and includes a voltage comparator circuit (12). A capacitor (20) is connected to an input terminal (14) of the voltage comparator circuit (12). A resistor divider network (30) is coupled to an input terminal (16) of the voltage comparator circuit (12) for generating a reference voltage. A delay circuit (50, 52) is coupled to an output terminal (42) of the voltage comparator circuit (12). A discharge device (54) is coupled to the delay circuit (50, 52) and to the capacitor (20) for discharging the capacitor (20). A switching device (40) is coupled to the output (42) of the voltage comparator circuit (12) and to the resistor divider network (30) for controlling the application of the reference voltage to voltage comparator circuit (12).

摘要翻译： 提供了一个电阻 - 电容振荡器电路（10）并包括电压比较器电路（12）。 电容器（20）连接到电压比较器电路（12）的输入端子（14）。 电阻分压器网络（30）耦合到电压比较器电路（12）的输入端子（16），用于产生参考电压。 延迟电路（50,52）耦合到电压比较器电路（12）的输出端子（42）。 放电装置（54）耦合到延迟电路（50,52）和电容器（20），用于对电容器（20）进行放电。 开关装置（40）耦合到电压比较器电路（12）的输出端（42）和电阻分压器网络（30），用于控制参考电压施加到电压比较器电路（12）。