公开(公告)号：WO2015179137A1

公开(公告)日：2015-11-26

申请号：PCT/US2015/029756

申请日：2015-05-07

Applicant: QUALCOMM INCORPORATED

Inventor： KONG, Derui ,  LEE, Sang Min ,  MCGOWAN, Michael Joseph ,  SEO, Dongwon

IPC: H03F1/14 ,  H03F3/45

CPC classification number: H03K17/16 ,  H03F1/14 ,  H03F3/45188

Abstract: A method and apparatus are provided. The apparatus may be a capacitive element for adjusting a net capacitance of a circuit. The apparatus may be configured to be coupled to the circuit. The apparatus may be configured to adjust the net capacitance of the circuit to decouple common mode and differential loop bandwidth adjustment of the circuit. The capacitive element may include a pair of cross-coupled capacitors configured to be coupled to differential nodes of the circuit, and a pair of negative gain buffers coupled to respective capacitors.

Abstract translation: 提供了一种方法和装置。 该装置可以是用于调整电路的净电容的电容元件。 该装置可以被配置为耦合到该电路。 该装置可以被配置为调整电路的净电容以去耦合电路的共模和差分环路带宽调整。 电容元件可以包括配置为耦合到电路的差分节点的一对交叉耦合电容器，以及耦合到相应电容器的一对负增益缓冲器。

公开(公告)号：WO2014138098A1

公开(公告)日：2014-09-12

申请号：PCT/US2014/020373

申请日：2014-03-04

Applicant: QUALCOMM INCORPORATED

Inventor： SEO, Dongwon ,  LEE, Sang Min

IPC: H03M1/08 ,  H03M1/68 ,  H03M1/74 ,  H03M1/78

CPC classification number: H03M1/785 ,  H03M1/0863 ,  H03M1/687 ,  H03M1/747

Abstract: An N-bit digital-to-analog converter (DAC) includes N input stages each of which generates the same amount of current and includes a pair of similarly sized transistor switches responsive to differential bits. The 2M-1 input stages associated with the M most significant bits of the DAC are connected in parallel and deliver their currents differentially to the DAC's current summing nodes. Each of the remaining (N-M) stages includes a resistive network that supplies a current defined by a binary weight of the stage's bit position within the DAC. The (N-M) stages deliver their currents to the current summing nodes differentially. The DAC further includes an impedance attenuator adapted to maintain the impedance of the current summing nodes and the voltage difference between the current summing nodes within a range defined by a gain of a differential amplifier disposed in the impedance attenuator.

Abstract translation: N位数模转换器（DAC）包括N个输入级，每个输入级产生相同量的电流，并且包括响应于差分位的一对类似尺寸的晶体管开关。 与DAC的M个最高有效位相关联的2M-1个输入级并联连接，并将其电流差分地传递给DAC的当前求和节点。 剩余（N-M）级中的每一个包括电阻网络，其提供由DAC内的级位位置的二进制权重定义的电流。 （N-M）级将它们的电流差分地传递到当前求和节点。 DAC还包括阻抗衰减器，其适于在由设置在阻抗衰减器中的差分放大器的增益限定的范围内保持电流求和节点的阻抗和电流求和节点之间的电压差。

公开(公告)号：WO2011041612A1

公开(公告)日：2011-04-07

申请号：PCT/US2010/051007

申请日：2010-09-30

Applicant: QUALCOMM INCORPORATED ,  SEO, Dongwon ,  SARIPALLI, Ganesh ,  SONG, Tongyu ,  TALEIE, Shahin, Mehdizad ,  KONG, Derui

Inventor： SEO, Dongwon ,  SARIPALLI, Ganesh ,  SONG, Tongyu ,  TALEIE, Shahin, Mehdizad ,  KONG, Derui

IPC: H03M1/74

CPC classification number: H03M1/742 ,  H03F1/223 ,  H03F1/3241 ,  H03F3/195 ,  H03F3/245 ,  H03F3/45183

Abstract: A circuit for digital-to-analog conversion is described. The circuit includes a digital-to-analog converter (DAC). The DAC includes a double cascaded current source and a differential current-mode switch (DCMS). The circuit further includes a direct current (DC) offset stage. The circuit also includes a load attenuator. The double cascaded current source may be between the DCMS and a rail voltage.

Abstract translation: 描述用于数模转换的电路。 该电路包括一个数模转换器（DAC）。 DAC包括双级联电流源和差分电流模式开关（DCMS）。 电路还包括直流（DC）偏置级。 该电路还包括负载衰减器。 双级联电流源可以在DCMS和导轨电压之间。

公开(公告)号：WO2008137752A1

公开(公告)日：2008-11-13

申请号：PCT/US2008/062515

申请日：2008-05-02

Applicant: QUALCOMM Incorporated ,  DABAG, Hayg-Taniel ,  MCALLISTER, Gene, H. ,  SEO, Dongwon

Inventor： DABAG, Hayg-Taniel ,  MCALLISTER, Gene, H. ,  SEO, Dongwon

IPC: H03M1/06 ,  H03M1/74

CPC classification number: H03M1/0665 ,  H03M1/0673 ,  H03M1/74 ,  H03M3/502

Abstract: Techniques for dynamically selecting circuit elements to combat mismatches are described. In one design, an apparatus includes first, second, and third circuits. The first circuit receives input data and provides first signals that are asserted based on the input data, e.g., with thermometer decoding. The second circuit receives the first signals and provides second signals used to select circuit elements, e.g., current sources, capacitors, resistors, etc. The third circuit generates a control for the second circuit, and the second circuit maps the first signals to the second signals based on this control. In one design, the second circuit includes a set of multiplexers and a control circuit. The multiplexers provides the first signals, circularly rotated by an amount determined by the control, as the second signals. The control circuit accumulates control data (e.g., the input data, pseudo-random data, or a fixed value) with the current control value to obtain new control value.

Abstract translation: 描述了用于动态选择电路元件以抵抗不匹配的技术。 在一种设计中，装置包括第一，第二和第三电路。 第一电路接收输入数据并提供基于输入数据而被确定的第一信号，例如用温度计解码。 第二电路接收第一信号并提供用于选择电路元件的第二信号，例如电流源，电容器，电阻器等。第三电路产生用于第二电路的控制，第二电路将第一信号映射到第二信号 基于此控制的信号。 在一种设计中，第二电路包括一组多路复用器和一个控制电路。 复用器提供循环旋转了由控制确定的量的第一信号作为第二信号。 控制电路用当前控制值累积控制数据（例如，输入数据，伪随机数据或固定值）以获得新的控制值。

公开(公告)号：WO2006036900A1

公开(公告)日：2006-04-06

申请号：PCT/US2005/034441

申请日：2005-09-22

Applicant: QUALCOMM INCORPORATED ,  SEO, Dongwon

Inventor： SEO, Dongwon

IPC: H03M1/06 ,  H03F1/32

CPC classification number: H03K17/04106 ,  H03M1/745

Abstract: A high-speed, high-accuracy DAC has multiple current switches. Each current switch includes a current source that provides a reference current, first and second circuit elements that couple to the current source, and first and second transistors that couple to the first and second circuit elements, respectively. The first transistor provides the reference current to a first output when enabled, and the second transistor provides the reference current to a second output when enabled. The first and second circuit elements provide source degeneration for the first and second transistors, extend the linear operating region for these transistors, and may be implemented with either transistors that are always turned on or resistors. The first and second transistors and the first and second circuit elements may be P-channel field effect transistors (P-FETs), N-channel field effect transistors (N-FETs), or transistors of some other type.

Abstract translation: 高速，高精度DAC具有多个电流开关。 每个电流开关包括提供耦合到电流源的参考电流，第一和第二电路元件以及耦合到第一和第二电路元件的第一和第二晶体管的电流源。 当使能时，第一晶体管将参考电流提供给第一输出，并且当使能时，第二晶体管将参考电流提供给第二输出。 第一和第二电路元件为第一和第二晶体管提供源极退化，扩展这些晶体管的线性工作区域，并且可以通过总是导通的晶体管或电阻来实现。 第一和第二晶体管以及第一和第二电路元件可以是P沟道场效应晶体管（P-FET），N沟道场效应晶体管（N-FET）或其他类型的晶体管。

公开(公告)号：WO2023049634A1

公开(公告)日：2023-03-30

申请号：PCT/US2022/076245

申请日：2022-09-09

Applicant: QUALCOMM INCORPORATED

Inventor： TANG, Zhilong ,  SEO, Dongwon

IPC: H03M1/10 ,  H03M1/74

Abstract: Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) system. The DAC system generally includes a plurality of current sources, a plurality of calibration DACs, each coupled to a respective one of the plurality of current sources, a reference current source, and a current mirror having a first branch selectively coupled to the plurality of current sources, wherein a second branch of the current mirror is coupled to the reference current source. The DAC system also includes a first error DAC selectively coupled to the first branch and the second branch of the current mirror, and a second error DAC selectively coupled to the first branch and the second branch of the current mirror.

公开(公告)号：WO2018208428A1

公开(公告)日：2018-11-15

申请号：PCT/US2018/027319

申请日：2018-04-12

Applicant: QUALCOMM INCORPORATED

Inventor： GUO, Wei ,  LEE, Sang Min ,  SEDIGHI, Behnam ,  SEO, Dongwon

IPC: H03M1/08 ,  H03M1/06 ,  H03M1/74 ,  H03M1/78

CPC classification number: H03M1/785 ,  H03M1/00 ,  H03M1/0607 ,  H03M1/08 ,  H03M1/742 ,  H03M1/747

Abstract: The present disclosure describes aspects of current removal for digital-to- analog converters (DACs). In some aspects, a circuit for converting a digital input to an analog output includes a first resistor ladder having first resistors connectable to respective current sources and connected to a first output of the circuit. The circuit also includes second resistor ladder having second resistors connectable to the respective current sources and connected to a second output of the circuit. A common node is formed between common resistor terminals of the first resistor ladder and the second resistor ladder. Current removal circuitry is connected to the common node and referenced to an amount of current provided by the respective current sources. By removing current from the common node of the resistor ladders, common-mode current at outputs of the circuit can be reduced with minimal degradation of differential performance of the circuit.

公开(公告)号：WO2016137768A1

公开(公告)日：2016-09-01

申请号：PCT/US2016/017815

申请日：2016-02-12

Applicant: QUALCOMM INCORPORATED

Inventor： SEO, Dongwon ,  YOU, Yang ,  JI, Honghao ,  SONG, Tongyu ,  SARIPALLI, Ganesh ,  MEHDIZAD TALEIE, Shahin

IPC: G05F1/56 ,  G05F1/575

CPC classification number: H03M1/0604 ,  G05F1/56 ,  G05F1/575 ,  G05F3/18 ,  H02M3/156 ,  H03F3/24 ,  H03M1/00 ,  H03M1/70 ,  H03M1/747 ,  H04B1/0475 ,  H04B2001/0408

Abstract: A method and apparatus for attenuating transmit digital to analog converter (DAC) spurs is provided. The method begins when a reference voltage is injected into an amplifier. Next, an output of the ground low drop-out regulator is measured and is them compared with the reference voltage. The output of the amplifier is then adjusted based on the results of the comparison. If the reference voltage is higher then the output of the ground low drop-out regulator the output of the amplifier is adjusted to ground. If the reference voltage is lower than the output of the ground low drop-out regulator then the output of the amplifier is adjusted to match the reference voltage.

Abstract translation: 提供了用于衰减发射数模转换器（DAC）杂散的方法和装置。 当将参考电压注入放大器时，该方法开始。 接下来，测量接地低压降稳压器的输出，并将其与参考电压进行比较。 然后根据比较结果调整放大器的输出。 如果参考电压较高，则接地低压降稳压器的输出将放大器的输出调整到地。 如果参考电压低于接地低压降稳压器的输出，则调节放大器的输出以匹配参考电压。

公开(公告)号：WO2016049288A1

公开(公告)日：2016-03-31

申请号：PCT/US2015/051893

申请日：2015-09-24

Applicant: QUALCOMM INCORPORATED

Inventor： DU, Li ,  LEE, Sang Min ,  SEO, Dongwon

IPC: G05F1/56

CPC classification number: H03G3/3042 ,  G05F1/561 ,  H03F1/0233 ,  H03F3/193 ,  H03F3/21 ,  H03F2200/21 ,  H03F2200/252 ,  H03F2200/451 ,  H03K5/24

Abstract: A converter including: an amplifier having first and second input terminals and an output terminal, the first input terminal configured to receive a reference voltage; an array of resistors configured to generate a tuning voltage; and a first plurality of switches coupled to the second input terminal of the amplifier and the array of resistors, the first plurality of switches configured to adjust a gain of the amplifier by selecting at least one resistor in the array of resistors to connect to the second input terminal of the amplifier.

Abstract translation: A转换器，包括：放大器，具有第一和第二输入端子和输出端子，所述第一输入端子被配置为接收参考电压; 配置成产生调谐电压的电阻阵列; 以及耦合到所述放大器的第二输入端子和所述电阻器阵列的第一多个开关，所述第一多个开关被配置为通过选择所述电阻器阵列中的至少一个电阻器来调节所述放大器的增益，以连接到所述第二 放大器的输入端。

公开(公告)号：WO2014150838A1

公开(公告)日：2014-09-25

申请号：PCT/US2014/024370

申请日：2014-03-12

Applicant: QUALCOMM INCORPORATED

Inventor： SONG, Tongyu ,  LEE, Sang Min ,  KONG, Derui ,  SEO, Dongwon

IPC: H03M1/06 ,  H03F3/45 ,  H03M1/74

CPC classification number: H03M1/74 ,  H03F3/19 ,  H03F3/211 ,  H03F3/245 ,  H03F3/45192 ,  H03F3/4565 ,  H03F3/72 ,  H03F2203/45466 ,  H03F2203/45512 ,  H03F2203/45562 ,  H03F2203/45631 ,  H03F2203/45634 ,  H03F2203/45644 ,  H03F2203/45686 ,  H03F2203/45701 ,  H03F2203/45702 ,  H03F2203/7236 ,  H03M1/0614

Abstract: A digital-to-analog converter (DAC) includes, in part, a multitude of input stages that supply currents to a pair of current summing nodes in response to a digital signal, and an impedance attenuator coupled between the current summing nodes and the output of the DAC. The impedance attenuator is adapted, among other function, to increase the range of impedances of the output load, to account for changes in the output load impedance due to variations in the process, voltage and temperature, and to decouple the impedances seen by the summing nodes from the load impedance. The impedance attenuator further includes a differential-input, differential-output amplifier with programmable common-mode gain bandwidth to control the harmonic distortion of the amplifier. The impedance attenuator optionally includes a pair of cross-coupled capacitors to control the harmonic distortion of the amplifier.

Abstract translation: 数模转换器（DAC）部分地包括响应于数字信号向一对当前求和节点提供电流的多个输入级，以及耦合在当前求和节点和输出端之间的阻抗衰减器 的DAC。 除了其他功能之外，阻抗衰减器还适用于增加输出负载的阻抗范围，以解决由于工艺，电压和温度的变化而导致的输出负载阻抗的变化，并且将由求和所看到的阻抗解耦 节点从负载阻抗。 阻抗衰减器还包括具有可编程共模增益带宽的差分输入差分输出放大器，以控制放大器的谐波失真。 阻抗衰减器可选地包括一对交叉耦合电容器，以控制放大器的谐波失真。