公开(公告)号：WO2014150838A1

公开(公告)日：2014-09-25

申请号：PCT/US2014/024370

申请日：2014-03-12

Applicant: QUALCOMM INCORPORATED

Inventor： SONG, Tongyu ,  LEE, Sang Min ,  KONG, Derui ,  SEO, Dongwon

IPC: H03M1/06 ,  H03F3/45 ,  H03M1/74

CPC classification number: H03M1/74 ,  H03F3/19 ,  H03F3/211 ,  H03F3/245 ,  H03F3/45192 ,  H03F3/4565 ,  H03F3/72 ,  H03F2203/45466 ,  H03F2203/45512 ,  H03F2203/45562 ,  H03F2203/45631 ,  H03F2203/45634 ,  H03F2203/45644 ,  H03F2203/45686 ,  H03F2203/45701 ,  H03F2203/45702 ,  H03F2203/7236 ,  H03M1/0614

Abstract: A digital-to-analog converter (DAC) includes, in part, a multitude of input stages that supply currents to a pair of current summing nodes in response to a digital signal, and an impedance attenuator coupled between the current summing nodes and the output of the DAC. The impedance attenuator is adapted, among other function, to increase the range of impedances of the output load, to account for changes in the output load impedance due to variations in the process, voltage and temperature, and to decouple the impedances seen by the summing nodes from the load impedance. The impedance attenuator further includes a differential-input, differential-output amplifier with programmable common-mode gain bandwidth to control the harmonic distortion of the amplifier. The impedance attenuator optionally includes a pair of cross-coupled capacitors to control the harmonic distortion of the amplifier.

Abstract translation: 数模转换器（DAC）部分地包括响应于数字信号向一对当前求和节点提供电流的多个输入级，以及耦合在当前求和节点和输出端之间的阻抗衰减器 的DAC。 除了其他功能之外，阻抗衰减器还适用于增加输出负载的阻抗范围，以解决由于工艺，电压和温度的变化而导致的输出负载阻抗的变化，并且将由求和所看到的阻抗解耦 节点从负载阻抗。 阻抗衰减器还包括具有可编程共模增益带宽的差分输入差分输出放大器，以控制放大器的谐波失真。 阻抗衰减器可选地包括一对交叉耦合电容器，以控制放大器的谐波失真。

公开(公告)号：WO2015179137A1

公开(公告)日：2015-11-26

申请号：PCT/US2015/029756

申请日：2015-05-07

Applicant: QUALCOMM INCORPORATED

Inventor： KONG, Derui ,  LEE, Sang Min ,  MCGOWAN, Michael Joseph ,  SEO, Dongwon

IPC: H03F1/14 ,  H03F3/45

CPC classification number: H03K17/16 ,  H03F1/14 ,  H03F3/45188

Abstract: A method and apparatus are provided. The apparatus may be a capacitive element for adjusting a net capacitance of a circuit. The apparatus may be configured to be coupled to the circuit. The apparatus may be configured to adjust the net capacitance of the circuit to decouple common mode and differential loop bandwidth adjustment of the circuit. The capacitive element may include a pair of cross-coupled capacitors configured to be coupled to differential nodes of the circuit, and a pair of negative gain buffers coupled to respective capacitors.

Abstract translation: 提供了一种方法和装置。 该装置可以是用于调整电路的净电容的电容元件。 该装置可以被配置为耦合到该电路。 该装置可以被配置为调整电路的净电容以去耦合电路的共模和差分环路带宽调整。 电容元件可以包括配置为耦合到电路的差分节点的一对交叉耦合电容器，以及耦合到相应电容器的一对负增益缓冲器。

公开(公告)号：WO2015167816A1

公开(公告)日：2015-11-05

申请号：PCT/US2015/026237

申请日：2015-04-16

Applicant: QUALCOMM INCORPORATED

Inventor： SONG, Tongyu ,  KONG, Derui

IPC: H03M1/10 ,  H03M1/74

CPC classification number: H03M1/1047 ,  H03M1/1057 ,  H03M1/68 ,  H03M1/742

Abstract: In an aspect of the disclosure, a method and an apparatus are provided for calibrating a DAC. The apparatus calibrates a first DAC element, provides a residual current error resulting from the calibration, the residual current error being a difference between a calibrated current source of the first DAC element and a reference current source, stores the residual current error of the calibrated first DAC element in a first memory module using at least first and second storage elements coupled to a differential amplifier, and calibrates a second DAC element using the stored residual current error.

Abstract translation: 在本公开的一方面，提供了一种用于校准DAC的方法和装置。 该装置校准第一DAC元件，提供由校准导致的剩余电流误差，剩余电流误差是第一DAC元件的校准电流源与参考电流源之间的差，存储校准的第一个 DAC元件，其使用至少第一和第二存储元件耦合到差分放大器，并且使用所存储的剩余电流误差来校准第二DAC元件。

公开(公告)号：WO2011041612A1

公开(公告)日：2011-04-07

申请号：PCT/US2010/051007

申请日：2010-09-30

Applicant: QUALCOMM INCORPORATED ,  SEO, Dongwon ,  SARIPALLI, Ganesh ,  SONG, Tongyu ,  TALEIE, Shahin, Mehdizad ,  KONG, Derui

Inventor： SEO, Dongwon ,  SARIPALLI, Ganesh ,  SONG, Tongyu ,  TALEIE, Shahin, Mehdizad ,  KONG, Derui

IPC: H03M1/74

CPC classification number: H03M1/742 ,  H03F1/223 ,  H03F1/3241 ,  H03F3/195 ,  H03F3/245 ,  H03F3/45183

Abstract: A circuit for digital-to-analog conversion is described. The circuit includes a digital-to-analog converter (DAC). The DAC includes a double cascaded current source and a differential current-mode switch (DCMS). The circuit further includes a direct current (DC) offset stage. The circuit also includes a load attenuator. The double cascaded current source may be between the DCMS and a rail voltage.

Abstract translation: 描述用于数模转换的电路。 该电路包括一个数模转换器（DAC）。 DAC包括双级联电流源和差分电流模式开关（DCMS）。 电路还包括直流（DC）偏置级。 该电路还包括负载衰减器。 双级联电流源可以在DCMS和导轨电压之间。