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    SYSTEM AND METHOD FOR VALIDATING COMPONENTS DURING A BOOTING PROCESS
    12.
    发明申请
    SYSTEM AND METHOD FOR VALIDATING COMPONENTS DURING A BOOTING PROCESS 审中-公开
    用于在钻孔过程中检验组件的系统和方法

    公开(公告)号：WO2013009619A8

    公开(公告)日：2014-01-23

    申请号：PCT/US2012045753

    申请日：2012-07-06

    Applicant: OPENPEAK INC ,  BROWN JOHN R ,  PERRET-GENTIL JOHN IRWIN

    Inventor： BROWN JOHN R ,  PERRET-GENTIL JOHN IRWIN

    IPC: G06F9/22 ,  G06F1/26 ,  G06F9/24 ,  G06F9/44

    CPC classification number: G06F21/575 ,  G06F9/4403 ,  G06F21/71 ,  G06F21/74 ,  G06F2221/2105

    Abstract: A method and system for validating components during a booting process of a computing device are described herein. The method can include the steps of detecting a power up signal and in response to detecting the power up signal, progressively determining whether software components of the computing device are valid. If the software components are determined to be valid, the computing device may be permitted to move to an operational state. If, however, at least some of the software components are determined to be not valid, the computing device may be prevented from moving to the operational state. In one arrangement, if the computing device is prevented from moving to the operational state, corrective action can be taken in an effort to permit the computing device to move to the operational state.

    Abstract translation: 本文描述了在计算设备的引导过程期间验证组件的方法和系统。 该方法可以包括检测上电信号和响应于检测到上电信号的步骤，逐步确定计算设备的软件组件是否有效。 如果软件组件被确定为有效，则可以允许计算设备移动到操作状态。 然而，如果至少一些软件组件被确定为无效，则可以防止计算设备移动到操作状态。 在一种布置中，如果计算设备被阻止移动到操作状态，则可以采取校正动作来努力允许计算设备移动到操作状态。

    INITIALIZATION OF MULTI-CORE PROCESSING SYSTEM
    14.
    发明申请
    INITIALIZATION OF MULTI-CORE PROCESSING SYSTEM 审中-公开
    多核处理系统的初始化

    公开(公告)号：WO2013101093A1

    公开(公告)日：2013-07-04

    申请号：PCT/US2011/067900

    申请日：2011-12-29

    Applicant: INTEL CORPORATION ,  CHANG, Steven, S. ,  THAKUR, Anshuman ,  SUNDARARAMAN, Ramacharan Charan ,  MATAS, Ramon

    Inventor： CHANG, Steven, S. ,  THAKUR, Anshuman ,  SUNDARARAMAN, Ramacharan Charan ,  MATAS, Ramon

    IPC: G06F15/80 ,  G06F13/14

    CPC classification number: G06F9/4405 ,  G06F1/24 ,  G06F9/4403 ,  G06F11/0724 ,  G06F12/0813 ,  G06F13/00 ,  G06F13/14 ,  G06F15/177 ,  G06F15/80

    Abstract: This disclosure is directed to use of shared initialization and configuration vectors, which are delivered to processing cores in a multi-core processor using packets. An initialization core may include reset logic that may read initialization and configuration vectors from a centralized storage location, which may be on a die containing the processing cores (e.g., a fuse, etc.), off the die (e.g., in volatile memory, flash memory, etc.), or a combination of both. The initialization core may then generate packets to transmit the initialization and configuration vectors to processing cores that await initialization (e.g., following a reset). In some instances, the initialization and configuration vector information may be shared by two or more cores of a same type.

    Abstract translation: 本公开涉及使用共享的初始化和配置向量，其被传递到使用分组的多核处理器中的处理核心。 初始化核心可以包括复位逻辑，其可以从集中存储位置读取初始化和配置向量，集中存储位置可以在包含处理核心（例如，熔丝等）的管芯上，例如在易失性存储器中， 闪存等），或两者的组合。 初始化内核然后可以生成分组以将初始化和配置向量传送到等待初始化（例如，重置之后）的处理核。 在一些情况下，初始化和配置向量信息可以由相同类型的两个或多个核共享。

    启动恢复的方法和装置
    17.
    发明申请
    启动恢复的方法和装置 审中-公开

    公开(公告)号：WO2012163029A1

    公开(公告)日：2012-12-06

    申请号：PCT/CN2011/081504

    申请日：2011-10-28

    Applicant: 华为技术有限公司 ,  侯国良

    Inventor： 侯国良

    IPC: G06F9/445

    CPC classification number: G06F9/4403

    Abstract: 本发明实施例提供了一种启动恢复的方法和装置，涉及启动恢复技术领域，所述方法包括：当引导操作系统时，使能高级配置和电源管理接口ACPI功能，将硬盘的配置信息备份到闪存只读存储器FlashROM中；当再次操作系统且引导失败时，将所述FlashROM内备份的硬盘的配置信息加载到硬盘启动操作系统，或通过所述FlashROM内备份的硬盘的配置信息启动操作系统。所述装置包括：备份模块和恢复模块。本发明实现了硬盘的自动备份以及快速启动恢复，操作简单，极大地降低了对操作人员的要求，提高了启动恢复的成功率。

    ROBUST AND HIGH-SPEED MEMORY ACCESS WITH ADAPTIVE INTERFACE TIMING
    20.
    发明申请
    ROBUST AND HIGH-SPEED MEMORY ACCESS WITH ADAPTIVE INTERFACE TIMING 审中-公开
    具有自适应接口时序的稳定和高速存储器访问

    公开(公告)号：WO2006055717A2

    公开(公告)日：2006-05-26

    申请号：PCT/US2005/041692

    申请日：2005-11-16

    Applicant: QUALCOMM INCORPORATED ,  CHUN, Dexter Tamio ,  PATIL, Ajit ,  HUANG, Ian ,  CHAN, Jason ,  GOLD, Timothy

    Inventor： CHUN, Dexter Tamio ,  PATIL, Ajit ,  HUANG, Ian ,  CHAN, Jason ,  GOLD, Timothy

    IPC: G11C7/10

    CPC classification number: G11C29/028 ,  G06F9/4403 ,  G06F9/44505 ,  G06F11/1068 ,  G11C7/1006 ,  G11C7/1045 ,  G11C7/22 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/32 ,  G11C29/42 ,  G11C29/50 ,  G11C29/50012 ,  G11C2216/14

    Abstract: Techniques for quickly and reliably accessing a memory device (e.g., a NAND Flash memory) with adaptive interface timing are described. For memory access with adaptive interface timing, the NAND Flash memory is accessed at an initial memory access rate, which may be the rate predicted to achieve reliable memory access. Error correction coding (ECC), which is often employed for NAND Flash memory, is then used to ensure reliable access of the NAND Flash. For a read operation, one page of data is read at a time from the NAND Flash memory, and the ECC determines whether the page read from the NAND Flash memory contains any errors. If errors are encountered, then a slower memory access rate is selected, and the page with error is read again from the NAND Flash memory at the new rate. The techniques may be used to write data to the NAND Flash memory.

    Abstract translation: 描述了利用自适应接口定时快速可靠地访问存储器件（例如，NAND闪存）的技术。 对于具有自适应接口定时的存储器访问，NAND闪存以初始存储器访问速率访问，其可以是预测的速率以实现可靠的存储器访问。 然后，通常用于NAND闪存的纠错编码（ECC）用于确保NAND闪存的可靠访问。 对于读取操作，从NAND闪速存储器一次读取一页数据，并且ECC确定从NAND闪速存储器读取的页面是否包含任何错误。 如果遇到错误，则选择较慢的存储器访问速率，并以新的速率从NAND闪存再次读取带有错误的页面。 这些技术可以用于将数据写入NAND闪存。

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